D/A Converter. DAC5573 Datasheet

DAC5573 Converter. Datasheet pdf. Equivalent

Part DAC5573
Description Quad 8-Bit D/A Converter
Feature www.ti.com DAC5573 SLAS401 – NOVEMBER 2003 2QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, I C INTERFACE D.
Manufacture etcTI
Datasheet
Download DAC5573 Datasheet



DAC5573
www.ti.com
DAC5573
SLAS401 – NOVEMBER 2003
2QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT,
I C INTERFACE DIGITAL-TO-ANALOG CONVERTER
FEATURES
Micropower Operation: 500 µA at 3 V VDD
Fast Update Rate: 188 kSPS
Power-On Reset to Zero
2.7-V to 5.5-V Analog Power Supply
8-Bit Monotonic
I2C™ Interface up to 3.4 Mbps
Data Transmit Capability
Rail-to-Rail Output Buffer Amplifier
Double-Buffered Input Register
Address Support for up to Sixteen DAC5573s
Synchronous Update for up to 64 Channels
Voltage Translators for all Digital Inputs
Operation From –40°C to 105°C
Small 16 Lead TSSOP Package
APPLICATIONS
Process Control
Data Acquisition Systems
Closed-Loop Servo Control
PC Peripherals
Portable Instrumentation
VDD IOVDD
DESCRIPTION
The DAC5573 is a low-power, quad channel, 8-bit
buffered voltage output DAC. Its on-chip precision
output amplifier allows rail-to-rail output swing. The
DAC5573 utilizes an I2C-compatible two-wire serial
interface supporting high-speed interface mode with
address support of up to sixteen DAC5573s for a total
of 64 channels on the bus.
The DAC5573 requires an external reference voltage
to set the output range of the DAC. The DAC5573
incorporates a power-on-reset circuit that ensures
that the DAC output powers up at zero volts and
remains there until a valid write takes place in the
device. The DAC5573 contains a power-down fea-
ture, accessed via the internal control register, that
reduces the current consumption of the device to 200
nA at 5 V.
The low power consumption of this part in normal
operation makes it ideally suited to portable battery
operated equipment. The power consumption is less
than 3 mW at VDD = 5 V reducing to 1 µW in
power-down mode.
The DAC5573 is available in a 16-lead TSSOP
package.
VREFH
Data
Buffer A
DAC
Register A
DAC A
Data
Buffer D
DAC
Register D
DAC D
18
VOUTA
VOUTB
VOUTC
VOUTD
SCL
SDA
I2C Block
Buffer
Control
8
Register
Control
A0 A1 GND
A2 A3 LDAC
VREFL
Power−Down
Control Logic
Resistor
Network
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Philips Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003, Texas Instruments Incorporated



DAC5573
DAC5573
SLAS401 – NOVEMBER 2003
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PRODUCT PACKAGE
DAC5573
16-TSSOP
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
PW
SPECIFICATION
TEMPERATURE
RANGE
–40°C TO +105°C
PACKAGE
MARKING
D5573I
ORDERING
NUMBER
DAC5573IPW
DAC5573IPWR
TRANSPORT MEDIA
90 Piece Tube
2000 Piece Tape and Reel
PW PACKAGE
(TOPVIEW)
VOUTA 1
VOUTB 2
VREFH 3
VDD 4
VREFL 5
GND 6
VOUTC 7
VOUTD 8
DAC5573
16 A3
15 A2
14 A1
13 A0
12 IOVDD
11 SDA
10 SCL
9 LDAC
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1
VOUTA Analog output voltage from DAC A
2
VOUTB Analog output voltage from DAC B
3
VREFH Positive reference voltage input
4
VDD Analog voltage supply input
5
VREFL Negative reference voltage input
6
GND
Ground reference point for all circuitry on the
part
7 VOUTC Analog output voltage from DAC C
8 VOUTD Analog output voltage from DAC D
9
LDAC H/W synchronous VOUT update
10
SCL Serial clock input
11
SDA Serial data input
12 IOVDD I/O voltage supply input
13
A0 Device address select - I2C
14
A1 Device address select - I2C
15
A2 Device address select - Extended
16
A3 Device address select - Extended
ABSOLUTE MAXIMUM RATINGS(1)
VDD to GND
Digital input voltage to GND
VOUT to GND
Operating temperature range
Storage temperature range
Junction temperature range (TJ max)
Power dissipation:
Thermal impedance (RΘJA)
Thermal impedance (RΘJC)
Lead temperature, soldering: Vapor phase (60s)
Infrared (15s)
–0.3 V to +6 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–40°C to +105°C
–65°C to +150°C
+150°C
161°C/W
29°C/W
215°C
220°C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2







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