8-LINE DECODERS/DEMULTIPLEXERS. 74F138 Datasheet

74F138 DECODERS/DEMULTIPLEXERS. Datasheet pdf. Equivalent


Part 74F138
Description 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
Feature SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D Designed Specifically for High-Speed .
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74F138 1-of-8 Decoder/Demultiplexer April 1988 Revised July 74F138 Datasheet
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SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS 74F138 Datasheet
Recommendation Recommendation Datasheet 74F138 Datasheet




74F138
SN54F138, SN74F138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
D Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
D Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
D Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
The F138 is designed to be used in
high-performance memory-decoding or data-
routing applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this decoder
and the enable time of the memory are usually
less than the typical access time of the memory.
This means that the effective system delay
introduced by the decoder is negligible.
SDFS051B – MARCH 1987 – REVISED JULY 1996
SN54F138 . . . J PACKAGE
SN74F138 . . . D OR N PACKAGE
(TOP VIEW)
A1
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
GND 8
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
SN54F138 . . . FK PACKAGE
(TOP VIEW)
C
G2A
NC
G2B
G1
3 2 1 20 19
4
18 Y1
5
17 Y2
6
16 NC
7
15 Y3
8
14 Y4
9 10 11 12 13
The conditions at the binary-select inputs and the
three enable inputs select one of eight output
lines. Two active-low and one active-high enable
inputs reduce the need for external gates or
NC – No internal connection
inverters when expanding. A 24-line decoder can
be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can
be used as a data input for demultiplexing applications.
The SN54F138 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74F138 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
1



74F138
SN54F138, SN74F138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDFS051B – MARCH 1987 – REVISED JULY 1996
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1 G2A G2B C
B
A
Y0 Y1 Y2 Y3 Y4 Y5 Y6
X
H
X
X
X
X
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
logic symbols (alternatives)
1
A
2
B
3
C
6
G1
4
G2A
5
G2B
BIN/OCT
1
0
2
1
4
2
3
&
4
EN
5
6
7
15
Y0
14
Y1
13
Y2
12
Y3
11
Y4
10
Y5
9
Y6
7
Y7
1
A
2
B
3
C
6
G1
4
G2A
5
G2B
DMUX
0
0
G
0
7
1
2
2
3
&
4
5
6
7
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Y7
H
H
H
H
H
H
H
H
H
H
L
15
Y0
14
Y1
13
Y2
12
Y3
11
Y4
10
Y5
9
Y6
7
Y7
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265







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