Protocol Transceiver. DP83630 Datasheet

DP83630 Transceiver. Datasheet pdf. Equivalent


etcTI DP83630
DP83630
www.ti.com
SNLS335B – OCTOBER 2010 – REVISED APRIL 2013
DP83630 Precision PHYTER™ - IEEE 1588 Precision Time Protocol Transceiver
Check for Samples: DP83630
1 Introduction
1.1 Features
123
• IEEE 1588 V1 and V2 Supported
• UDP/IPv4, UDP/IPv6, and Layer2 Ethernet
Packets Supported
• IEEE 1588 Clock Synchronization
• Selectable Frequency Synchronized Low Jitter
Clock Output
• Timestamp Resolution of 8 ns
• Allows Sub 10 ns Synchronization to Master
Reference
• 12 IEEE 1588 GPIOs for Trigger or Capture
• Deterministic, Low Transmit and Receive
Latency
• Dynamic Link Quality Monitoring
• TDR Based Cable Diagnostic and Cable Length
Detection
• 10/100 Mb/s Packet BIST (Built in Self Test)
• Error-Free Operation up to 150 Meters CAT5
Cable
• ESD Protection - 8 kV Human Body Model
• 2.5 V and 3.3 V I/Os and MAC Interface
• Auto-MDIX for 10/100 Mbps
• Auto-Crossover in Forced Modes of Operation
• RMII Rev. 1.2 and MII MAC Interface
• RMII Master Mode
• 25 MHz MDC and MDIO Serial Management
Interface
• IEEE 802.3u 100BASE-FX Fiber Interface
• IEEE 1149.1 JTAG
• Programmable LED Support for Link, 10 /100
Mb/s Mode, Duplex, Activity, and Collision
Detect
• Optional 100BASE-TX Fast Link-Loss Detection
• Industrial Temperature Range
• 48 Pin WQFN Package (7mm) x (7mm)
1.2 Applications
• Telecom
– Basestation
– Pico/Femto Cells
• Factory Automation
– Ethernet/IP
– CIP Sync
• Test and Measurement
– LXI Standard
• Video Synchronization
• Real Time Networking
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PHYTER is a trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated


DP83630 Datasheet
Recommendation DP83630 Datasheet
Part DP83630
Description IEEE 1588 Precision Time Protocol Transceiver
Feature DP83630; DP83630 www.ti.com SNLS335B – OCTOBER 2010 – REVISED APRIL 2013 DP83630 Precision PHYTER™ - IEEE .
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etcTI DP83630
DP83630
SNLS335B – OCTOBER 2010 – REVISED APRIL 2013
www.ti.com
1.3 Description
The DP83630 Precision PHYTER™ device delivers the highest level of precision clock synchronization for
real time industrial connectivity based on the IEEE 1588 standard. The DP83630 has deterministic, low
latency and allows choice of microcontroller with no hardware customization required. The integrated 1588
functionality allows system designers the flexibility and precision of a close to the wire timestamp. The
three key 1588 features supported by the device are:
— Packet time stamps for clock synchronization
— Integrated IEEE 1588 synchronized low jitter clock generation
— Synchronized event triggering and time stamping through GPIO
DP83630 offers innovative diagnostic features unique to Texas Instruments, including dynamic monitoring
of link quality during standard operation for fault prediction. These advanced features allow the system
designer to implement a fault prediction mechanism to detect and warn of deteriorating and changing link
conditions. This single port fast Ethernet transceiver can support both copper and fiber media.
2
Introduction
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Copyright © 2010–2013, Texas Instruments Incorporated



etcTI DP83630
DP83630
www.ti.com
1 Introduction .............................................. 1
1.1 Features ............................................. 1
1.2 Applications .......................................... 1
1.3 Description ........................................... 2
2 Device Information ...................................... 5
2.1 System Diagram ..................................... 5
2.2 Block Diagram ....................................... 5
2.3 Key IEEE 1588 Features ............................ 6
3 Pin Descriptions ....................................... 10
3.1 Pin Layout .......................................... 11
3.2 PACKAGE PIN ASSIGNMENTS ................... 12
3.3 SERIAL MANAGEMENT INTERFACE ............. 13
3.4 MAC DATA INTERFACE ........................... 13
3.5 CLOCK INTERFACE ............................... 14
3.6 LED INTERFACE .................................. 15
3.7 IEEE 1588 EVENT/TRIGGER/CLOCK INTERFACE
...................................................... 15
3.8 JTAG INTERFACE ................................. 15
3.9 RESET AND POWER DOWN ...................... 16
3.10 STRAP OPTIONS .................................. 16
3.11 10 Mb/s AND 100 Mb/s PMD INTERFACE ........ 18
3.12 POWER SUPPLY PINS ............................ 18
4 Electrical Specifications ............................. 19
4.1 Absolute Maximum Ratings ........................ 19
4.2 Recommended Operating Conditions .............. 19
4.3 AC and DC Specifications .......................... 19
4.4 DC Specifications .................................. 20
4.5 AC Specifications — Power Up Timing ............ 21
4.6 AC Specifications — Reset Timing ................. 22
4.7 AC Specifications — MII Serial Management Timing
...................................................... 23
4.8 AC Specifications — 100 Mb/s MII Transmit Timing
...................................................... 23
4.9 AC Specifications — 100 Mb/s MII Receive Timing 23
4.10 AC Specifications — 100BASE-TX and 100BASE-
FX MII Transmit Packet Latency Timing ........... 24
4.11 AC Specifications — 100BASE-TX and 100BASE-
FX MII Transmit Packet Deassertion Timing ....... 24
4.12 AC Specifications — 100BASE-TX Transmit Timing
(tR/F & Jitter) ........................................ 25
4.13 AC Specifications — 100BASE-TX and 100BASE-
FX MII Receive Packet Latency Timing ............ 25
4.14 AC Specifications — 100BASE-TX and 100BASE-
FX MII Receive Packet Deassertion Timing ....... 26
4.15 AC Specifications — 10 Mb/s MII Transmit Timing 26
4.16 AC Specifications — 10 Mb/s MII Receive Timing . 26
4.17 AC Specifications — 10BASE-T MII Transmit
Timing (Start of Packet) ............................ 27
4.18 AC Specifications — 10BASE-T MII Transmit
Timing (End of Packet) ............................. 27
4.19 AC Specifications — 10BASE-T MII Receive Timing
(Start of Packet) .................................... 28
4.20 AC Specifications — 10BASE-T MII Receive Timing
(End of Packet) ..................................... 28
4.21 AC Specifications — 10 Mb/s Heartbeat Timing ... 28
4.22 AC Specifications — 10 Mb/s Jabber Timing ...... 29
SNLS335B – OCTOBER 2010 – REVISED APRIL 2013
4.23 AC Specifications — 10BASE-T Normal Link Pulse
Timing .............................................. 29
4.24 AC Specifications — Auto-Negotiation Fast Link
Pulse (FLP) Timing ................................. 29
4.25 AC Specifications — 100BASE-TX Signal Detect
Timing .............................................. 30
4.26 AC Specifications — 100 Mb/s Internal Loopback
Timing .............................................. 30
4.27 AC Specifications — 10 Mb/s Internal Loopback
Timing .............................................. 31
4.28 AC Specifications — RMII Transmit Timing (Slave
Mode) ............................................... 31
4.29 AC Specifications — RMII Transmit Timing (Master
Mode) ............................................... 32
4.30 AC Specifications — RMII Receive Timing (Slave
Mode) ............................................... 33
4.31 AC Specifications — RMII Receive Timing (Master
Mode) ............................................... 34
4.32 AC Specifications — RX_CLK Timing (RMII Master
Mode) ............................................... 34
4.33 AC Specifications — CLK_OUT Timing (RMII Slave
Mode) ............................................... 35
4.34 AC Specifications — Single Clock MII (SCMII)
Transmit Timing .................................... 35
4.35 AC Specifications — Single Clock MII (SCMII)
Receive Timing ..................................... 36
4.36 AC Specifications — 100 Mb/s X1 to TX_CLK
Timing .............................................. 36
5 Configuration ........................................... 37
5.1 MEDIA CONFIGURATION ......................... 37
5.2 AUTO-NEGOTIATION .............................. 37
5.3 AUTO-MDIX ........................................ 40
5.4 AUTO-CROSSOVER IN FORCED MODE ......... 40
5.5 PHY ADDRESS .................................... 40
5.6 LED INTERFACE ................................... 41
5.7 HALF DUPLEX vs. FULL DUPLEX ................ 43
5.8 INTERNAL LOOPBACK ............................ 44
5.9 POWER DOWN/INTERRUPT ...................... 44
5.10 ENERGY DETECT MODE ......................... 44
5.11 LINK DIAGNOSTIC CAPABILITIES ................ 45
5.12 BIST ................................................ 49
6 MAC Interface .......................................... 50
6.1 MII INTERFACE .................................... 50
6.2 REDUCED MII INTERFACE ....................... 51
6.3 SINGLE CLOCK MII MODE ........................ 52
6.4 IEEE 802.3u MII SERIAL MANAGEMENT
INTERFACE ........................................ 53
6.5 PHY CONTROL FRAMES ......................... 54
6.6 PHY STATUS FRAMES ............................ 55
7 Architecture ............................................. 56
7.1 100BASE-TX TRANSMITTER ...................... 56
7.2 100BASE-TX RECEIVER .......................... 59
7.3 100BASE-FX OPERATION ......................... 63
7.4 10BASE-T TRANSCEIVER MODULE .............. 64
8 Reset Operation ........................................ 67
8.1 HARDWARE RESET ............................... 67
8.2 FULL SOFTWARE RESET ......................... 67
Copyright © 2010–2013, Texas Instruments Incorporated
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Product Folder Links: DP83630
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