Schmitt Trigger. 14093BG Datasheet

14093BG Trigger. Datasheet pdf. Equivalent

14093BG Datasheet
Recommendation 14093BG Datasheet
Part 14093BG
Description Quad 2-Input NAND Schmitt Trigger
Feature 14093BG; MC14093B Quad 2-Input “NAND" Schmitt Trigger The MC14093B Schmitt trigger is constructed with MOS .
Manufacture ON Semiconductor
Datasheet
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ON Semiconductor 14093BG
MC14093B
Quad 2-Input “NAND"
Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2−input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature
Range
Triple Diode Protection on All Inputs
Pin−for−Pin Compatible with CD4093
Can be Used to Replace MC14011B
Independent Schmitt−Trigger at each Input
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
±10
mA
PD Power Dissipation,
per Package (Note 1)
500
mW
TA
Ambient Temperature Range
Tstg Storage Temperature Range
TL
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
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SOIC−14
D SUFFIX
CASE 751A
SOEIAJ−14
F SUFFIX
CASE 965
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
IN 1A 1
IN 2A 2
OUTA 3
OUTB 4
IN 1B 5
IN 2B 6
VSS 7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
MARKING DIAGRAMS
14
14
14093BG
AWLYWW
MC14093B
ALYWG
1
SOIC−14
1
SOEIAJ−14
14
14
093B
ALYW G
G
1
TSSOP−14
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 10
Publication Order Number:
MC14093B/D



ON Semiconductor 14093BG
MC14093B
LOGIC DIAGRAM
1
2
3
5
6
4
8
9
10
12
13
11
VDD = PIN 14
VSS = PIN 7
EQUIVALENT CIRCUIT SCHEMATIC
(1/4 OF CIRCUIT SHOWN)
ORDERING INFORMATION
Device
Package
Shipping
MC14093BDG
SOIC−14
(Pb−Free)
55 Units / Rail
NLV14093BDG*
SOIC−14
(Pb−Free)
55 Units / Rail
MC14093BDR2G
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
NLV14093BDR2G*
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
MC14093BDTR2G
TSSOP−14
(Pb−Free)
2500 Units / Tape & Reel
NLV14093BDTR2G*
TSSOP−14
(Pb−Free)
2500 Units / Tape & Reel
MC14093BFELG
SOEIAJ−14
(Pb−Free)
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2



ON Semiconductor 14093BG
MC14093B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
−55_C
25_C
125_C
Characteristic
VDD
Typ
Symbol Vdc
Min
Max
Min (Note 2) Max
Min
Max Unit
Output Voltage
Vin = VDD or 0
“0” Level VOL
5.0
10
15
0.05
0.05
0.05
0
0.05
0.05 Vdc
0
0.05
0.05
0
0.05
0.05
Vin = 0 or VDD
“1” Level VOH
5.0
4.95
4.95
5.0
10
9.95
9.95
10
15 14.95
14.95
15
4.95
Vdc
9.95
14.95
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
Input Capacitance
(Vin = 0)
Quiescent Current
(Per Package)
IOH
Source
Sink IOL
Iin
Cin
IDD
5.0
–3.0
–2.4
–4.2
5.0 –0.64
–0.51 –0.88
10
–1.6
–1.3
–2.25
15
–4.2
–3.4
–8.8
mAdc
–1.7
–0.36
–0.9
–2.4
5.0
0.64
0.51
0.88
10
1.6
1.3
2.25
15
4.2
3.4
8.8
0.36
− mAdc
0.9
2.4
15
±0.1
±0.00001 ±0.1
±1.0 mAdc
5.0
7.5
pF
5.0
0.25
0.0005 0.25
7.5 mAdc
10
0.5
0.0010
0.5
15
15
1.0
0.0015
1.0
30
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
IT = (1.2 mA/kHz) f + IDD
IT = (2.4 mA/kHz) f + IDD
IT = (3.6 mA/kHz) f + IDD
mAdc
Hysteresis Voltage
VH
5.0
0.3
2.0
0.3
1.1
2.0
0.3
2.0 Vdc
10
1.2
3.4
1.2
1.7
3.4
1.2
3.4
15
1.6
5.0
1.6
2.1
5.0
1.6
5.0
Threshold Voltage
Positive−Going
Vdc
VT+
5.0
2.2
3.6
2.2
2.9
3.6
2.2
3.6
10
4.6
7.1
4.6
5.9
7.1
4.6
7.1
15
6.8
10.8
6.8
8.8
10.8
6.8
10.8
Negative−Going
VT–
5.0
0.9
2.8
0.9
1.9
2.8
0.9
2.8 Vdc
10
2.5
5.2
2.5
3.9
5.2
2.5
5.2
15
4.0
7.4
4.0
5.8
7.4
4.0
7.4
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
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