Bus Transceiver. TC7LX1102WBG Datasheet
CMOS Digital Integrated Circuits Silicon Monolithic
1. Functional Description
• Low-Voltage, Low-Power 2-Bit Dual-Supply Bus Transceiver with Auto Direction Sensing
The TC7LX1102WBG is an advanced high-speed dual-supply 2-bit bus transceiver fabricated with silicon-gate
The TC7LX1102WBG is designed for use as an interface between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-
V voltage systems.
The voltage translator automatically senses the direction of data transmission, eliminating the need for a direction
control input. When the Output Enable (OE) input is low, the device is disabled, effectively isolating the buses.
All inputs and outputs of the TC7LX1102WBG can tolerate overvoltage conditions up to 3.6 V.
(1) Voltage translation between arbitrary voltage levels from 1.2 V to 3.6 V.
(2) High-speed operation: tpd = 5.0 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 3.3 ± 0.3 V)
(3) Latch-up performance: ±300 mA
(4) ESD performance:
Machine model ≥ ±200 V, Human body model ≥ ±2000 V
(5) Ultra-small package: WCSP8B
(6) The A-bus and B-bus are allowed to float. (when OE = Low)
(7) 3.6-V tolerant function and power-down protection provided on all inputs and outputs.
(8) All output ports are disabled when either VCC is switched off (VCCA/B=0V)
4. Packaging and Pin Assignment (Top View)
4.1. Pin Assignment
6. Block Diagram
Fig. 5.1 Marking
Fig. 6.1 Block Diagram
7. Internal Equivalent Circuit
The TC7LX1102WBG does not have a control signal that controls the direction of data flow between A and B. In
a DC state, the output circuit holds either High or Low level, but since it is designed to have a weak drive strength
(with a typical output resistance of 5.5 kΩ), an overdrive signal from the external driver can change the direction
of data flow.
The output one-shot circuits detect either a rising or falling edge on the A or B port. During the rise time, the
output one-shot circuit associated with the PMOS transistors turns it on for a certain period to speed up a
transition from Low to High. Likewise, during the fall time, the output one-shot circuit associated with the NMOS
transistors turns it on to speed up a transition from High to Low.
Fig. 7.1 Internal Equivalent Circuit
8. Principle of Operation
8.1. Truth Table
A port = B port