Monostable Multivibrator. TC7WH123FK Datasheet

TC7WH123FK Multivibrator. Datasheet pdf. Equivalent

TC7WH123FK Datasheet
Recommendation TC7WH123FK Datasheet
Part TC7WH123FK
Description Monostable Multivibrator
Feature TC7WH123FK; TC7WH123FU/FK TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC7WH123FU, TC7WH123FK Mon.
Manufacture Toshiba
Datasheet
Download TC7WH123FK Datasheet




Toshiba TC7WH123FK
TC7WH123FU/FK
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC7WH123FU, TC7WH123FK
Monostable Multivibrator
The TC7WH123 is high speed CMOS MONOSTABLE
MULTIVIBRATOR fabricated with silicon gate C2MOS technology.
There are two trigger inputs, A input (Negative edge), and B
input (Positive edge). These inputs are valid for a slow rise/fall time
signal (tr = tf = 1 s) as they are schmitt trigger inputs. This device
may also be triggered by using CLR input (Positive edge).
After triggering, the output stays in a MONOSTABLE state for a
time period determined by the external resistor and capacitor (RX,
CX). A low level at the CLR input breaks this state.
Limits for CX and RX are:
External capacitor, CX: No limit
External resistor, RX: VCC = 2.0 V more than 5 kΩ
VCC 3.0 V more than 1 kΩ
An input protection circuit ensures that 0 to 7 V can be applied to
the input pins without regard to the supply voltage. This device can
be used to interface 5 V to 3 V systems and two supply systems
such as battery back up. This circuit prevents device destruction
due to mismatched supply and input voltages.
TC7WH123FU
TC7WH123FK
Weight
SSOP8-P-0.65
SSOP8-P-0.50A
: 0.02 g (typ.)
: 0.01 g (typ.)
Features
High speed: tpd = 8.1 ns (typ.) at VCC = 5 V
Low power dissipation
Standby state: ICC = 2 μA (max) at Ta = 25°C
Active state : ICC = 650 μA (max) at VCC = 4.5 V
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power down protection is equipped with all inputs.
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2 to 5.5 V
Start of commercial production
1998-08
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Toshiba TC7WH123FK
Marking
SM8
H123
Type Name
US8
Lot No.
WH
123
Truth Table
Inputs
A
B CLR
H
H
X
L
H
H
X
H
L
H
L
H
X
X
L
X: Don’t care
Outputs
Q
L
L
L
Block Diagram
Note
Output Enable
Inhibit
Inhibit
Output Enable
Output Enable
Reset
TC7WH123FU/FK
Pin Assignment (top view)
VCC RX/CX CX
Q
8
7
6
5
1
2
3
4
A
B CLR GND
IEC Logic Symbol
Note: CX, RX, DX are external capacitor, resistor, and diode, respectively.
Note:
External clamping diode, DX;
The external capacitor is charged to VCC level in the wait state, i.e. when no trigger is applied.
If the supply voltage is turned off, CX is discharges mainly through the internal (parasitic) diode. If CX is
sufficiently large and VCC drops rapidly, there will be some possibility of damaging the IC through in rush
current or latch-up. If the capacitance of the supply voltage filter is large enough and VCC drops slowly, the in
rush current is automatically limited and damage to the IC is avoided.
The maximum value of forward current through the parasitic diode is ±20 mA.
In the case of a large CX, the limit of fall time of the supply voltage is determined as follows:
tf (VCC - 0.7) CX / 20 mA
(tf is the time between the supply voltage turn off and the supply voltage reaching 0.4 VCC.)
In the even a system does not satisfy the above condition, an external clamping diode (DX) is needed to protect
the IC from rush current.
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Toshiba TC7WH123FK
TC7WH123FU/FK
Functional Description
(1) Standby state
The external capacitor (CX) is fully charged to VCC in the stand-by state. That means, before triggering,
the QP and QN transistors which are connected to the RX/CX node are in the off state. Two comparators
that relate to the timing of the output pulse, and two reference voltage supplies turn off. The total supply
current is only leakage current.
(2) Trigger operation
Trigger operation is effective in any of the following three cases. First, the condition where the A input
is low, and the B input has a rising signal; second, where the B input is high, and the A input has a falling
signal; and third, where the A input is low and the B input is high, and the CLR input has a rising signal.
After a trigger becomes effective, comparators C1 and C2 start operating, and QN is turned on. The
external capacitor discharges through QN. The voltage level at the RX/CX node drops. If the RX/CX voltage
level falls to the internal reference voltage VrefL, the output of C1 becomes low. The flip-flop is then reset
and QN turns off. At that moment C1 stops but C2 continues operating.
After QN turns off, the voltage at the RX/CX node starts rising at a rate determined by the time constant of
external capacitor CX and resistor RX.
Upon triggering, output Q becomes high, following some delay time of the internal F/F and gates. It stays
high even if the voltage of RX/CX changes from falling to rising. When RX/CX reaches the internal reference
voltage VrefH, the output of C2 becomes low, the output Q goes low and C2 stops its operation. That means,
after triggering, when the voltage level of the RX/CX node reaches VrefH, the IC returns to its
MONOSTABLE state.
With large values of CX and RX, and ignoring the discharge time of the capacitor and internal delays of
the IC, the width of the output pulse, tw OUT, is as follows:
twOUT = 1.0 · CX · RX
(3) Retrigger operation
When a new trigger is applied to either input A or B while in the MONOSTABLE state, it is effective only
if the IC is charging CX. The voltage level of the RX/CX node then falls to VrefL level again. Therefore the Q
output stays high if the next trigger comes in before the time period set by CX and RX.
If the new trigger is very close to previous trigger, such as an occurrence during the discharge cycle, it will
have no effect.
The minimum time for a trigger to be effective 2nd trigger, trr (min), depends on VCC and CX.
(4) Reset operation
In normal operation, the CLR input is held high. If CLR is low, a trigger has no effect because the Q
output is held low and the trigger control F/F is reset. Also, QP turns on and CX is charged rapidly to VCC.
This means if CLR is set low, the IC goes into a wait state.
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