Stereo ADC. TLV320ADC3101-Q1 Datasheet

TLV320ADC3101-Q1 ADC. Datasheet pdf. Equivalent


etcTI TLV320ADC3101-Q1
www.ti.com
TLV320ADC3101-Q1
SLAS816B – MARCH 2012 – REVISED AUGUST 2012
Low-Power Stereo ADC With Embedded miniDSP
for Wireless Handsets and Portable Audio
Check for Samples: TLV320ADC3101-Q1
FEATURES
1
2 Qualified for Automotive Applications
• AEC-Q100 Test Guidance With the Following
Results:
– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H1C
– Device CDM ESD Classification Level C3B
• Stereo Audio ADC
– 92-dBA Signal-to-Noise Ratio
– Supports ADC Sample Rates From 8 kHz to
96 kHz
• Instruction-Programmable Embedded miniDSP
• Flexible Digital Filtering With RAM
Programmable Coefficient, Instructions, and
Built-In Processing Blocks
– Low-Latency IIR Filters for Voice
– Linear Phase FIR Filters for Audio
– Additional Programmable IIR Filters for EQ,
Noise Cancellation or Reduction
– Up to 128 Programmable ADC Digital Filter
Coefficients
• Six Audio Inputs With Configurable Automatic
Gain Control (AGC)
– Programmable in Single-Ended or Fully
Differential Configurations
– Can Be 3-Stated for Easy Interoperability
With Other Audio ICs
• Low Power Consumption and Extensive
Modular Power Control:
– 6-mW Mono Record, 8-kHz
– 11-mW Stereo Record, 8-kHz
– 10-mW Mono Record, 48-kHz
– 17-mW Stereo Record, 48-kHz
• Dual Programmable Microphone Bias
• Programmable PLL for Clock Generation
• I2C™ Control Bus
• Audio Serial Data Bus Supports I2S, Left/Right-
Justified, DSP, PCM, and TDM Modes
• Digital Microphone Input Support
• Two GPIOs
• Power Supplies:
– Analog: 2.6 V–3.6 V
– Digital: Core: 1.65 V–1.95 V,
I/O: 1.1 V–3.6 V
• 4-mm × 4-mm 24-Pin RGE (QFN)
APPLICATIONS
• Wireless Handsets
• Portable Low-Power Audio Systems
• Noise-Cancellation Systems
• Front-End Voice or Audio Processor for Digital
Audio
DESCRIPTION
The TLV320ADC3101-Q1 is a low-power, stereo
audio analog-to-digital converter (ADC) supporting
sampling rates from 8 kHz to 96 kHz with an
integrated programmable-gain amplifier providing up
to 40-dB analog gain or AGC. A programmable
miniDSP is provided for custom audio processing.
Front-end input coarse attenuation of 0 dB, –6 dB, or
off, is also provided. The inputs are programmable in
a combination of single-ended or fully differential
configurations. Extensive register-based power
control is available via an I2C interface, enabling
mono or stereo recording. Low power consumption
makes the TLV320ADC3101-Q1 ideal for battery-
powered portable equipment.
The AGC programs to a wide range of attack
(7 ms–1.4 s) and decay (50 ms–22.4 s) times. A
programmable noise-gate function is included to
avoid noise pumping. Low-latency IIR filters optimized
for voice and telephony are available, as well as
linear-phase FIR filters optimized for audio.
Programmable IIR filters are also available and may
be used for sound equalization, or to remove noise
components. The audio serial bus can be
programmed to support I2S, left-justified, right-
justified, DSP, PCM, and TDM modes. The audio bus
may be operated in either master or slave mode.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Phillips Electronics.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated


TLV320ADC3101-Q1 Datasheet
Recommendation TLV320ADC3101-Q1 Datasheet
Part TLV320ADC3101-Q1
Description Low-Power Stereo ADC
Feature TLV320ADC3101-Q1; www.ti.com TLV320ADC3101-Q1 SLAS816B – MARCH 2012 – REVISED AUGUST 2012 Low-Power Stereo ADC With .
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Datasheet
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etcTI TLV320ADC3101-Q1
TLV320ADC3101-Q1
SLAS816B – MARCH 2012 – REVISED AUGUST 2012
www.ti.com
DESCRIPTION (CONTINUED)
A programmable integrated PLL is included for flexible clock generation and provides support for all standard
audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, including the most popular
cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED BLOCK DIAGRAM
DINL
DINR
SDA
SCL
RESET
MCLK
MICBIAS2
MICBIAS1
DVSS
IOVDD
DVDD
AVSS
AVDD
Figure 1. TLV320ADC3101-Q1 Block Diagram
2
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etcTI TLV320ADC3101-Q1
www.ti.com
ORDERABLE P/N
6PADC3101TRGERQ1
TLV320ADC3101-Q1
SLAS816B – MARCH 2012 – REVISED AUGUST 2012
Table 1. ORDERING INFORMATION
TA
–40°C to 105°C
PACKAGE
VQFN (24) - RGE
Reel of 3000
TOP SIDE SYMBOL
ADC | 3101Q
PIN ASSIGNMENTS
TLV320ADC3101-Q1
RGE PACKAGE
(TOP VIEW)
BCLK 1
WCLK 2
DOUT 3
RESET 4
MICBIAS1 5
IN3L(M) 6
18 SDA
17 SCL
16 I2C_ADR1
15 I2C_ADR0
14 MICBIAS2
13 IN3R(M)
Connect the QFN thermal pad to AVSS.
PIN
NAME
AVDD
AVSS
BCLK
DMCLK/GPIO2
DMDIN/GPIO1
DOUT
DVDD
DVSS
I2C_ADR0
I2C_ADR1
IN1L(P)
IN1R(M)
NUMBER
10
9
1
20
19
3
22
23
15
16
8
11
PIN FUNCTIONS
DESCRIPTION
Analog voltage supply, 2.6 V–3.6 V
Analog ground supply, 0 V
Audio serial data bus bit clock (input/output)
Digital microphone clock / general-purpose input/output #2 (input/output) / PLL clock input
/ audio serial data-bus bit-clock input/output / multifunction pin based on register
programming
Digital microphone data input / general-purpose input/output #1 (input/output) / PLL clock
mux output / AGC noise flag / multifunction pin based on register programming
Audio serial data bus data output (output)
Digital core voltage supply, 1.65 V–1.95 V
Digital ground supply, 0 V
LSB of I2C bus address
LSB + 1 of I2C bus address
Mic or line analog input (left-channel single-ended or differential plus, or right channel)
Mic or line analog input (left-channel single-ended or differential minus, or left channel)
Copyright © 2012, Texas Instruments Incorporated
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