PCM Codec. TLV320AIC1106 Datasheet

TLV320AIC1106 Codec. Datasheet pdf. Equivalent


etcTI TLV320AIC1106
TLV320AIC1106
PCM CODEC
SLAS357 − DECEMBER 2001
FEATURES
D Designed for Analog and Digital Wireless
Handsets, Voice-Enabled Terminals, and
Telecommunications Applications
D 2.7-V to 3.3-V Operation
D Selectable 13-Bit Linear or 8-Bit µ-Law
Companded Conversion
D Differential Microphone Input With External
Gain Setting
D Differential Earphone Output Capable of
Driving a 32-to 8-Load
D Programmable Volume Control in Linear Mode
D Microphone (MIC) and Earphone (EAR) Mute
Functions
D Typical Power Dissipation of 0.03 mW in
Power-Down Mode
D 2.048-MHz Master Clock Rate
D 300-Hz to 3.4-kHz Passband
D Low Profile 20-Terminal TSSOP Packaging
APPLICATIONS
D Digital Handset
D Digital Headset
D Cordless Phones
D Digital PABX
D Digital Voice Recording
DESCRIPTION
The TLV320AIC1106 PCM codec is designed to
perform transmit encoding analog-to-digital (A/D)
conversion, receive decoding digital-to-analog (D/A)
conversion, and transmit and receive filtering for
voice-band communications systems. The
TLV320AIC1106 device operates in either the 13-bit
linear or 8-bit companded -law) mode. The PCM
codec generates its own internal clocks from a
2.048-MHz master clock input.
PW PACKAGE
(TOP VIEW)
MICMUTE
1
RESET
2
VSS
3
EARVSS
4
EAROUT+
5
EARVDD
6
EAROUT−
7
EARVSS
8
MICGAIN+
9
MICIN−
10
20
EARMUTE
19
MCLK
18
PCMSYNC
17
PCMO
16
PCMI
15
DVSS
14
DVDD
13
LINSEL
12
MICGAIN −
11
MICIN+
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright 2001, Texas Instruments Incorporated
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TLV320AIC1106 Datasheet
Recommendation TLV320AIC1106 Datasheet
Part TLV320AIC1106
Description PCM Codec
Feature TLV320AIC1106; TLV320AIC1106 PCM CODEC SLAS357 − DECEMBER 2001 FEATURES D Designed for Analog and Digital Wirele.
Manufacture etcTI
Datasheet
Download TLV320AIC1106 Datasheet




etcTI TLV320AIC1106
TLV320AIC1106
SLAS357 − DECEMBER 2001
functional block diagram
(16)
PCMI
PCMSYNC (18)
(19)
MCLK
PLL
MICGAIN −
MICIN +
MICIN −
(12)
MIC Amp 1
(11)
+
(10)
MICGAIN + (9)
MIC
Amp 2
(1)
MICMUTE
RESET
LINSEL
EARVDD
EARVSS
VSS
DVSS
DVDD
(2)
(13)
(6)
(8) (4)
(3)
(15)
(14)
Power
and
Reset
TX
Filter
PCM
Interface
RX
Volume
Control
(17)
PCMO
Analog
Modulator
RX
Filter
Digital
Modulator
and Filter
EAR
AMP
(5)
EAROUT+
(7)
EAROUT−
(20)
EARMUTE
RX = Receive
TX = Transmit
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etcTI TLV320AIC1106
TLV320AIC1106
SLAS357 − DECEMBER 2001
detailed description
power up/reset
An external reset must be applied to the active-low RESET terminal while MCLK is active to ensure reset at
power up.
reference
A precision band-gap reference voltage is generated internally and supplies all required references to operate
the transmit and receive channels.
phase-locked loop
The phase-locked loop generates the internal clock frequency required for internal digital filters and modulators
by phase-locking to 2.048-MHz master clock input.
PCM interface
The PCM interface transmits and receives data at the PCMO and PCMI terminals, respectively. The data is
transmitted or received at the MCLK speed once on each PCMSYN cycle. The PCMSYN can be driven by an
external source that is derived from the master clock and used as an interrupt to the host controller.
microphone input
The microphone input circuit consists of two differential input/differential output amplifiers (MIC Amp 1 and
MIC Amp 2). MIC Amp 1 is a low-noise differential amplifier capable of an externally set gain. MIC Amp 2 is a
differential amplifier with a fixed gain of 6 dB.
analog modulator
The transmit channel modulator is a third-order sigma-delta design.
transmit filter
The transmit filter is a digital filter designed to meet Consultive Committee on International Telegraphy and
Telephony (CCITT) G.714 requirements. The TLV320AIC1106 device operates in either the 13-bit linear or 8-bit
companded µ-law mode.
receive filter
The receive (RX) filter is a digital filter that meets CCITT G.714 requirements. The TLV320AIC1106 device
operates in either the 13-bit linear or 8-bit µ-law companded mode, which is selected at the LINSEL input.
receive volume control
In linear mode, the three least significant bits of the 16-bit PCMI data sample is used to control volume. The
volume range is −18 dB to 3 dB in 3-dB steps.
digital modulator and filter
The second-order digital modulator and filter convert the received digital PCM data to the analog output required
by the earphone interface.
earphone amplifiers
EAROUT is recommended for use as a differential output; however, it can be connected in single-ended
topology as well. Clicks and pops are suppressed from the differential output.
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