Inverting Buffer/Converter. CD4049UBF3A Datasheet

CD4049UBF3A Buffer/Converter. Datasheet pdf. Equivalent

CD4049UBF3A Datasheet
Recommendation CD4049UBF3A Datasheet
Part CD4049UBF3A
Description CMOS Hex Inverting Buffer/Converter
Feature CD4049UBF3A; www.ti.com CD4049UB, CD4050B SCHS046K – AUGUST 1C99D84–0R4E9VUISBE,DCJDUN4E052002B0 SCHS046K – AUGU.
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Datasheet
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Texas Instruments CD4049UBF3A
www.ti.com
CD4049UB, CD4050B
SCHS046K – AUGUST 1C99D840R4E9VUISBE,DCJDUN4E052002B0
SCHS046K – AUGUST 1998 – REVISED JUNE 2020
CD4049UB and CD4050B CMOS Hex Inverting Buffer and Converter
1 Features
• CD4049UB Inverting
• CD4050B Noninverting
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over Full
Package Temperature Range; 100 nA at 18 V and
25°C
• 5-V, 10-V, and 15-V Parametric Ratings
2 Applications
• CMOS to DTL or TTL Hex Converters
• CMOS Current Sink or Source Drivers
• CMOS High-to-Low Logic Level Converters
VCC
3 Description
The CD4049UB and CD4050B devices are inverting
and noninverting hex buffers, and feature logic-level
conversion using only one supply voltage (VCC). The
input-signal high level (VIH) can exceed the VCC
supply voltage when these devices are used for logic-
level conversions. These devices are intended for use
as CMOS to DTL or TTL converters and can drive
directly two DTL or TTL loads. (VCC = 5 V,
VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.)
Device Information
PART NUMBER(1)
CD4049UBE,
CD4050BE
CD4049UBD,
CD4050BD
CD4049UBDW,
CD4050BDW
CD4049UBNS,
CD4050BNS
CD4049UBPW,
CD4050BPW
PACKAGE
PDIP (16)
SOIC (16)
SOIC (16)
SO (16)
TSSOP (16)
BODY SIZE (NOM)
6.35 mm × 19.30 mm
9.90 mm × 3.91 mm
10.30 mm × 7.50 mm
10.30 mm × 5.30 mm
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VCC
R
IN
P
OUT
N
VSS
Copyright © 2016,
Texas Instruments Incorporated
1 of 6 Identical Units
Schematic Diagram of CD4049UB
R
IN
P
P
OUT
N
N
VSS
Copyright © 2016, Texas Instruments Incorporated
1 of 6 Identical Units
Schematic Diagram of CD4050B
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
Copyrighint t©el2le0c2t0uTael xparsoIpnesrtrtuymmeanttsteIrnscoarnpdoraottehder important disclaimers. PRODUCTION DATA.
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Product Folder Links: CD4049UB CD4050B



Texas Instruments CD4049UBF3A
CD4049UB, CD4050B
SCHS046K – AUGUST 1998 – REVISED JUNE 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: DC..................................... 5
6.6 Electrical Characteristics: AC......................................9
6.7 Typical Characteristics.............................................. 10
7 Parameter Measurement Information.......................... 11
7.1 Test Circuits...............................................................11
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 13
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................14
9 Application and Implementation.................................. 15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................16
11 Layout........................................................................... 16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Documentation Support.......................................... 17
12.2 Related Links.......................................................... 17
12.3 Receiving Notification of Documentation Updates..17
12.4 Support Resources................................................. 17
12.5 Trademarks............................................................. 17
12.6 Electrostatic Discharge Caution..............................17
12.7 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (September 2016) to Revision K (June 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated Device Information Table with correct package dimensions................................................................ 1
Changes from Revision I (May 2004) to Revision J (September 2016)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table; see POA at the end of the data sheet....................................................... 1
• Changed Storage temperature minimum value from 65 to –65..........................................................................4
• Changed RθJA values for the CD4049UB device: D (SOIC) from 73 to 81.6, DW (SOIC) from 57 to 81.6, E
(PDIP) from 67 to 49.5, NS (SO) from 64 to 84.3, and PW (TSSOP) from 108 to 108.9................................... 5
• Changed RθJA values for the CD4050B device: D (SOIC) from 73 to 81.6, DW (SOIC) from 57 to 81.2, E
(PDIP) from 67 to 49.7, NS (SO) from 64 to 83.8, and PW (TSSOP) from 108 to 108.4................................... 5
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Product Folder Links: CD4049UB CD4050B
Copyright © 2020 Texas Instruments Incorporated



Texas Instruments CD4049UBF3A
www.ti.com
5 Pin Configuration and Functions
CD4049UB, CD4050B
SCHS046K – AUGUST 1998 – REVISED JUNE 2020
VCC
1
G
2
A
3
H
4
B
5
I
6
C
7
VSS
8
16
NC
15
L
14
F
13
NC
12
K
11
E
10
J
9
D
VCC
1
G
2
A
3
H
4
B
5
I
6
C
7
VSS
8
16
NC
15
L
14
F
13
NC
12
K
11
E
10
J
9
D
Not to scale
Figure 5-1. CD4049UB D, DW, N, NS, and PW
Packages 16-Pin SOIC, PDIP, SO, and TSSOP Top
View
Not to scale
Figure 5-2. CD4050B D, DW, N, NS, and PW
Packages 1G6-Pin SOIC, PDIP, SO, and TSSOP Top
View
Pin Functions: CD4049UB
NAME
A
B
C
D
E
F
G
H
I
J
K
L
NC
VCC
VSS
PIN
NO.
3
5
7
9
11
14
2
4
6
10
12
15
13, 16
1
8
I/O
I
Input 1
I
Input 2
I
Input 3
I
Input 4
I
Input 5
I
Input 6
O Inverting output 1. G = A
O Inverting output 2. H = B
O Inverting output 3. I = C
O Inverting output 4. J = D
O Inverting output 5. K = E
O Inverting output 6. L = F
— No connection
— Power pin
— Negative supply
DESCRIPTION
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: CD4049UB CD4050B
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