Non-Synchronous Converter. TPS54386 Datasheet

TPS54386 Converter. Datasheet pdf. Equivalent

TPS54386 Datasheet
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Part TPS54386
Description Dual 3-A Non-Synchronous Converter
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TPS54383, TPS54386
SLUS774C – AUGUST 2007 – REVISED DECEMBER 2014
TPS5438x Dual 3-A Non-Synchronous Converters With Integrated High-Side MOSFET
1 Features
1 4.5-V to 28-V Input Range
• Output Voltage Range 0.8 V to 90% of Input
Voltage
• Output Current Up to 3 A
• Two Fixed Switching Frequency Versions:
– TPS54383: 300 kHz
– TPS54386: 600 kHz
• Three Selectable Levels of Overcurrent Protection
(Output 2)
• 0.8-V 1.5% Voltage Reference
• 2.1-ms Internal Soft-Start
• Dual PWM Outputs 180° Out-of-Phase
• Ratiometric or Sequential Startup Modes
Selectable by a Single Pin
• 85-mInternal High-Side MOSFETs
• Current Mode Control
• Internal Compensation (See Page 16)
• Pulse-by-Pulse Overcurrent Protection
• Thermal Shutdown Protection at +148°C
• 14-Pin PowerPAD™ HTSSOP package
2 Applications
• Set Top Box
• Digital TV
• Power for DSP
• Consumer Electronics
3 Description
The TPS54383 and TPS54386 are dual output, non-
synchronous buck converters capable of supporting
3-A output applications that operate from a 4.5-V to
28-V input supply voltage, and require output
voltages between 0.8 V and 90% of the input voltage.
With an internally-determined operating frequency,
soft-start time, and control loop compensation, these
converters provide many features with a minimum of
external components. Channel 1 overcurrent
protection is set at 4.5 A, while Channel 2 overcurrent
protection level is selected by connecting a pin to
ground, to BP, or left floating. The setting levels are
used to allow for scaling of external components for
applications that do not need the full load capability of
both outputs.
The outputs may be enabled independently, or may
be configured to allow either ratio-metric or sequential
startup sequencing. Additionally, the two outputs may
be powered from different sources.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS54383
TPS54386
HTSSOP (14)
4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
VIN
OUTPUT1
TPS54383
1 PVDD1 PVDD2 14
2 BOOT1 BOOT2 13
3 SW1
SW2 12
4 GND
BP 11
5 EN1
SEQ 10
6 EN2
ILIM2 9
7 FB1
FB2 8
GND
OUTPUT2
UDG-07123
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



etcTI TPS54386
TPS54383, TPS54386
SLUS774C – AUGUST 2007 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Typical Characteristics .............................................. 8
8 Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 29
9 Applications and Implementation ...................... 30
9.1 Application Information............................................ 30
9.2 Typical Applications ................................................ 30
10 Power Supply Recommendations ..................... 41
11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
11.2 Layout Example .................................................... 42
11.3 PowerPAD Package.............................................. 43
12 Device and Documentation Support ................. 44
12.1 Device Support...................................................... 44
12.2 Documentation Support ........................................ 45
12.3 Related Links ........................................................ 45
12.4 Trademarks ........................................................... 45
12.5 Electrostatic Discharge Caution ............................ 45
12.6 Glossary ................................................................ 45
13 Mechanical, Packaging, and Orderable
Information ........................................................... 46
5 Revision History
Changes from Revision B (October 2007) to Revision C
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
2
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Copyright © 2007–2014, Texas Instruments Incorporated
Product Folder Links: TPS54383 TPS54386



etcTI TPS54386
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6 Pin Configuration and Functions
PWP Package
14-Pin HTSSOP
Bottom View
PVDD1 1
BOOT1 2
SW1 3
GND 4
EN1 5
EN2 6
FB1 7
Thermal Pad
(bottom side)
TPS54383, TPS54386
SLUS774C – AUGUST 2007 – REVISED DECEMBER 2014
14 PVDD2
13 BOOT2
12 SW2
11 BP
10 SEQ
9 ILIM2
8 FB2
PIN
NAME
NO.
BOOT1
2
BOOT2
13
BP
11
EN1
5
EN2
6
FB1
7
FB2
8
GND
4
Pin Functions
I/O
DESCRIPTION
Input supply to the high side gate driver for Output 1. Connect a 22-nF to 82-nF capacitor from this pin
I
to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is
turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small
resistor (1 to 3 ) may be placed in series with the bootstrap capacitor.
Input supply to the high side gate driver for Output 2. Connect a 22-nF to 82-nF capacitor from this pin
I
to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is
turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small
resistor (1 to 3 ) may be placed in series with the bootstrap capacitor.
-
Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low ESR (4.7-μF
to 10-μF X7R or X5R) ceramic capacitor.
Active low enable input for Output 1. If the voltage on this pin is greater than 1.55 V, Output 1 is
I
disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 1 and allows soft-start
of Output 1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin
to GND for "always ON" operation.
Active low enable input for Output 2. If the voltage on this pin is greater than 1.55 V, Output 2 is
I
disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 2 and allows soft-start
of Output 2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin
to GND for "always ON" operation.
Voltage feedback pin for Output 1. The internal transconductance error amplifier adjusts the PWM for
Output 1 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from
I Output 1 to ground, with the center connection tied to this pin, determines the value of the regulated
output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback
Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information.
Voltage feedback pin for Output 2. The internal transconductance error amplifier adjusts the PWM for
Output 2 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from
I Output 2 to ground, with the center connection tied to this pin, determines the value of the regulated
Output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback
Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information.
- Ground pin for the device. Connect directly to Thermal Pad.
Copyright © 2007–2014, Texas Instruments Incorporated
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