Hex Inverter. CD74HCU04 Datasheet

CD74HCU04 Inverter. Datasheet pdf. Equivalent

CD74HCU04 Datasheet
Recommendation CD74HCU04 Datasheet
Part CD74HCU04
Description Hex Inverter
Feature CD74HCU04; CD74HCU04 Data sheet acquired from Harris Semiconductor SCHS127D February 1998 - Revised May 2004 .
Manufacture etcTI
Datasheet
Download CD74HCU04 Datasheet




Texas Instruments CD74HCU04
CD74HCU04
Data sheet acquired from Harris Semiconductor
SCHS127D
February 1998 - Revised May 2004
High-Speed CMOS Logic
Hex Inverter
[ /Title
(CD74
HCU04
)
/Sub-
ject
(High
Speed
CMOS
Logic
Hex
Inverter
Features
Description
• TCyLp=ic1a5l pPFr,oTpAag=a2ti5oonCD, Felaasyt:e6snt sPaarttVinCCQM= O5VS, Line
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HCU Types
- 2-V to 6-V Operation
- High Noise Immunity: NIL = 20%, NIH = 30% of
VCC at VCC = 5V
• CMOS Input Compatibility, Il 1µA at VOL, VOH
The CD74HCU04 unbuffered hex inverter utilizes silicon-gate
CMOS technology to achieve operation speeds similar to
LSTTL gates, with the low power consumption of standard
CMOS integrated circuits. These devices especially are useful
in crystal oscillator and analog applications.
Ordering Information
PART NUMBER
CD74HCU04E
CD74HCU04M
CD74HCU04MT
TEMP. RANGE
(oC)
PACKAGE
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
CD74HCU04M96
-55 to 125
14 Ld SOIC
CD74HCU04PWR
-55 to 125
14 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes
96 and R denote tape and reel. The suffix T denotes a small-
quantity reel of 250.
Pinout
CD74HCU04
(PDIP, SOIC, TSSOP)
TOP VIEW
1A 1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND 7
14 VCC
13 6A
12 6Y
11 5A
10 5Y
9 4A
8 4Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1



Texas Instruments CD74HCU04
Functional Diagram
CD74HCU04
1
1A
2
1Y
3
2A
4
2Y
5
3A
6
3Y
7
GND
14 VCC
13
6A
12
6Y
11 5A
10 5Y
9
4A
8
4Y
Logic Symbol
nA
nY
Schematic Diagram
VCC
(3, 5, 9, 11, 13) 1
2 (4, 6, 8, 10, 12)
2



Texas Instruments CD74HCU04
CD74HCU04
Absolute Maximum Ratings
DC Supply Voltage, VCC
Voltages Referenced to Ground . . . . . . . . . . . . . . . . -0.5V to +7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range TA. . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
SYMBOL
VIH
VIL
VOH
TEST
CONDITIONS
VI (V) IO (mA) VCC (V)
-
-
2
4.5
6
-
-
2
4.5
6
VIH or -0.02
2
VIL
-0.02
4.5
-0.02
6
VCC or
-4
4.5
GND
-5.2
6
VOL
VIH or 0.02
2
VIL
0.02
4.5
0.02
6
4
4.5
VCC or 5.2
6
GND
II
VCC or
-
6
GND
ICC
VCC or
0
6
GND
25oC
MIN MAX
1.7
-
3.6
-
4.8
-
-
0.3
-
0.8
-
1.1
1.8
-
4
-
5.5
-
3.98
-
5.48
-
-
0.2
-
0.5
-
0.5
-
0.26
-
0.26
-
±0.1
-
2
-40oC TO +85oC
MIN MAX
1.7
-
3.6
-
4.8
-
-
0.3
-
0.8
-
1.1
1.8
-
4
-
5.5
-
3.84
-
5.34
-
-55oC TO 125oC
MIN MAX
1.7
-
3.6
-
4.8
-
-
0.3
-
0.8
-
1.1
1.8
-
4
-
5.5
-
3.7
-
5.2
-
UNITS
V
V
V
V
V
V
V
V
V
V
V
-
0.2
-
0.2
V
-
0.5
-
0.5
V
-
0.5
-
0.5
V
-
0.33
-
0.4
V
-
0.33
-
0.4
V
-
±1
-
±1
µA
-
20
-
40
µA
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