Expansion Switch. 89HPES32T8G2 Datasheet

89HPES32T8G2 Switch. Datasheet pdf. Equivalent

89HPES32T8G2 Datasheet
Recommendation 89HPES32T8G2 Datasheet
Part 89HPES32T8G2
Description I/O Expansion Switch
Feature 89HPES32T8G2; 32-Lane 8-Port PCIe® Gen2 I/O Expansion Switch ® 89HPES32T8G2 Data Sheet Device Overview The 89HPE.
Manufacture Renesas
Datasheet
Download 89HPES32T8G2 Datasheet




Renesas 89HPES32T8G2
32-Lane 8-Port PCIe® Gen2
I/O Expansion Switch
®
89HPES32T8G2
Data Sheet
Device Overview
The 89HPES32T8G2 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES32T8G2 is a 32-lane, 8-port
switch optimized for PCI Express Gen2 packet switching in high-perfor-
mance applications. Target applications include servers, storage,
communications, embedded systems, and multi-host or intelligent I/O
based systems with inter-domain communication.
Features
High Performance Non-Blocking Switch Architecture
32-lane 8-port PCIe switch
• Four x8 switch ports each of which can bifurcate to two x4
ports (total of eight x4 ports)
Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s
Gen1 operation
Delivers up to 32 GBps (256 Gbps) of switching capacity
Supports 128 Bytes to 2 KB maximum payload size
Low latency cut-through architecture
Supports one virtual channel and eight traffic classes
Standards and Compatibility
PCI Express Base Specification 2.0 compliant
Implements the following optional PCI Express features
• Advanced Error Reporting (AER) on all ports
• End-to-End CRC (ECRC)
• Access Control Services (ACS)
• Power Budgeting Enhanced Capability
• Device Serial Number Enhanced Capability
• Sub-System ID and Sub-System Vendor ID Capability
• Internal Error Reporting ECN
• Multicast ECN
• VGA and ISA enable
• L0s and L1 ASPM
• ARI ECN
Port Configurability
x4 and x8 ports
• Ability to merge adjacent x4 ports to create a x8 port
Automatic per port link width negotiation
(x8 x4 x2 x1)
Crosslink support
Automatic lane reversal
Autonomous and software managed link width and speed
control
Per lane SerDes configuration
• De-emphasis
• Receive equalization
• Drive strength
Initialization / Configuration
Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
Common switch configurations are supported with pin strap-
ping (no external components)
Supports in-system Serial EEPROM initialization/program-
ming
Quality of Service (QoS)
Port arbitration
• Round robin
Request metering
• IDT proprietary feature that balances bandwidth among
switch ports for maximum system throughput
High performance switch core architecture
• Combined Input Output Queued (CIOQ) switch architecture
with large buffers
Multicast
Compliant to the PCI-SIG multicast ECN
Supports arbitrary multicasting of Posted transactions
Supports 64 multicast groups
Multicast overlay mechanism support
ECRC regeneration support
Clocking
Supports 100 MHz and 125 MHz reference clock frequencies
Flexible clocking modes
• Common clock
• Non-common clock
Hot-Plug and Hot Swap
Hot-plug controller on all ports
• Hot-plug supported on all downstream switch ports
All ports support hot-plug using low-cost external I2C I/O
expanders
Configurable presence detect supports card and cable appli-
cations
GPE output pin for hot-plug event notification
• Enables SCI/SMI generation for legacy operating system
support
Hot-swap capable I/O
Power Management
Supports D0, D3hot and D3 power management states
Active State Power Management (ASPM)
• Supports L0, L0s, L1, L2/L3 Ready and L3 link states
• Configurable L0s and L1 entry timers allow performance/
power-savings tuning
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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Renesas 89HPES32T8G2
IDT 89HPES32T8G2 Data Sheet
Supports PCI Express Power Budgeting Capability
SerDes power savings
• Supports low swing / half-swing SerDes operation
• SerDes optionally turned-off in D3hot
• SerDes associated with unused ports are turned-off
• SerDes associated with unused lanes are placed in a low
power state
9 General Purpose I/O
Reliability, Availability and Serviceability (RAS)
ECRC support
AER on all ports
SECDED ECC protection on all internal RAMs
End-to-end data path parity protection
Checksum Serial EEPROM content protected
Autonomous link reliability (preserves system operation in the
presence of faulty links)
Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
Test and Debug
On-chip link activity and status outputs available for Port 0
(upstream port)
Per port link activity and status outputs available using
external I2C I/O expander for all other ports
SerDes test modes
Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
Power Supplies
Requires only two power supply voltages (1.0 V and 2.5 V)
Note that a 3.3V is preferred for VDDI/O
No power sequencing requirements
Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with
1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES32T8G2
provides the most efficient fan-out solution for applications requiring
high throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 32 GBps (256 Gbps) of aggregated,
full-duplex switching capacity through 32 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 GT/s of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
The PES32T8G2 is based on a flexible and efficient layered archi-
tecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 2.0. The PES32T8G2 can operate either as a store and
forward or cut-through switch. It supports eight Traffic Classes (TCs)
and one Virtual Channel (VC) with sophisticated resource management
to enable efficient switching and I/O connectivity for servers, storage,
and embedded processors with limited connectivity.
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Renesas 89HPES32T8G2
IDT 89HPES32T8G2 Data Sheet
Block Diagram
I
Frame Buffer
8-Port Switch Core / 32 Gen2 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
(Port 0)
(Port 1)
(Port 7)
Figure 1 Internal Block Diagram
SMBus Interface
The PES32T8G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES32T8G2,
allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration
register values of the PES32T8G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is
also used by an external Hot-Plug I/O expander.
Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and
SSMBADDR2 pins. As shown in Figure 2, the master and slave SMBuses may only be used in a split configuration.
Switch
... Processor
SMBus
Other
SMBus
Master
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
Hot-Plug
I/O
Expander
Figure 2 Split SMBus Interface Configuration
The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the
SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two
independent buses; thus, multi-master arbitration is not required.
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