Clock Generator. MPC9773 Datasheet

MPC9773 Generator. Datasheet pdf. Equivalent

MPC9773 Datasheet
Recommendation MPC9773 Datasheet
Part MPC9773
Description LVCMOS PLL Clock Generator
Feature MPC9773; 3.3 V 1:12 LVCMOS PLL Clock Generator MPC9773 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIR.
Manufacture Renesas
Datasheet
Download MPC9773 Datasheet




Renesas MPC9773
3.3 V 1:12 LVCMOS PLL Clock Generator
MPC9773
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
DATASHEET
The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted
for high-performance low-skew clock distribution in mid-range to high-
performance networking, computing, and telecom applications. With output
frequencies up to 240 MHz and output skews less than 250 ps the device meets
the needs of the most demanding clock applications.
Features
• 1:12 PLL based low-voltage clock generator
• 3.3 V power supply
• Internal power-on reset
• Generates clock signals up to 242.5 MHz
• Maximum output skew of 250 ps
• Differential PECL reference clock input
• Two LVCMOS PLL reference clock inputs
• External PLL feedback supports zero-delay capability
• Various feedback and output dividers (refer to Application Section)
• Supports up to three individual generated output clock frequencies
• Synchronous output clock stop circuitry for each individual output for power
down support
• Drives up to 24 clock lines
• Ambient temperature range -40C to +85C
• Pin and function compatible to the MPC973
• 52-lead Pb-free package
• Use drop in replacement part 87973I
MPC9773
3.3 V 1:12 LVCMOS
PLL CLOCK GENERATOR
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 848D-03
Functional Description
The MPC9773 utilizes PLL technology to frequency lock its outputs onto an
input reference clock. Normal operation of the MPC9773 requires the connection
of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the
divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The
MPC9773 features an extensive level of frequency programmability between the 12 outputs as well as the output to input rela-
tionships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-
tion, the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-
binary factor. The MPC9773 also supports the 180phase shift of one of its output banks with respect to the other output banks.
The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system
baseline timing signals.
The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative
LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass con-
figuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers,
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics
do not apply.
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
MPC9773. The MPC9773 has an internal power-on reset.
The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission
lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
MPC9773 REVISION 6 MARCH 16, 2016
1
©2016 Integrated Device Technology, Inc.



Renesas MPC9773
MPC9773 Data Sheet
PCLK
PCLK
CCLK0
CCLK1
CCLK_SEL
All input resistors have a value of 25 k
1
VCC 0
0
1
VCC
Ref
VCO
PLL
200–485 MHz
0
2 0
1
1 1
4, 6, 8, 12
4, 6, 8, 10
2, 4, 6, 8
4, 6, 8, 10
12, 16, 20
SYNC PULSE
REF_SEL
FB_IN
VCO_SEL
PLL_EN
FSEL_A[0:1]
FSEL_B[0:1]
FSEL_C[0:1]
FSEL_FB[0:2]
FB
VCC
2
2
2
3
VCC
Power-On Reset
INV_CLK
STOP_DATA
STOP_CLK
MR/OE
Clock Stop
12
Figure 1. MPC9773 Logic Diagram
3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR
Bank A
CLK
Stop
Bank B
CLK
Stop
Bank C
CLK
Stop
0
CLK
1
Stop
CLK
Stop
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
QFB
QSYNC
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
VCC
QA2
GND
QA1
VCC
QA0
GND
VCO_SEL
4039 38 37 36 35 34 33 32 31 30 29 28 2726
41
25
42
24
43
23
44
22
45
21
46
MPC9773
20
47
19
48
18
49
17
50
16
51
15
52 1 2 3 4 5 6 7 8 9 10 11 12 1314
FSEL_FB1
QSYNC
GND
QC0
VCC
QC1
FSEL_C0
FSEL_C1
QC2
VCC
QC3
GND
INV_CLK
Figure 2. MPC9773 52-Lead Package Pinout (Top View)
MPC9773 REVISION 6 MARCH 16, 2016
2
©2016 Integrated Device Technology, Inc.



Renesas MPC9773
MPC9773 Data Sheet
3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR
Table 1. Pin Configuration
Pin
CCLK0
I/O
Input
CCLK1
PCLK, PCLK
Input
Input
FB_IN
Input
CCLK_SEL
Input
REF_SEL
Input
VCO_SEL
Input
PLL_EN
Input
MR/OE
Input
FSEL_A[0:1]
Input
FSEL_B[0:1]
Input
FSEL_C[0:1]
FSEL_FB[0:2]
Input
Input
INV_CLK
STOP_CLK
Input
Input
STOP_DATA
Input
QA[0-3]
Output
QB[0-3]
Output
QC[0-3]
Output
QFB
Output
QSYNC
Output
GND
Supply
VCC_PLL
Supply
VCC
Supply
Type
LVCMOS
LVCMOS
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
VCC
Function
PLL reference clock
Alternative PLL reference clock
Differential LVPECL reference clock
PLL feedback signal input, connect to an QFB
LVCMOS clock reference select
LVCMOS/PECL reference clock select
VCO operating frequency select
PLL enable/PLL bypass mode select
Output enable/disable (high-impedance tristate) and device reset
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
Frequency divider select for the QFB output
Clock phase selection for outputs QC2 and QC3
Clock input for clock stop circuitry
Configuration data input for clock stop circuitry
Clock outputs (Bank A)
Clock outputs (Bank B)
Clock outputs (Bank C)
PLL feedback output. Connect to FB_IN.
Synchronization pulse output
Negative power supply
PLL positive power supply (analog power supply). It is recommended to use an external RC
filter for the analog power supply pin VCC_PLL. Please refer to applications section for details.
Positive power supply for I/O and core. All VCC pins must be connected to the positive power
supply for correct operation
Table 2. Function Table (Configuration Controls)
Control Default
0
REF_SEL
1 Selects CCLKx as the PLL reference clock
1
Selects the LVPECL inputs as the PLL
reference clock
CCLK_SEL
VCO_SEL
PLL_EN
1 Selects CCLK0
Selects CCLK1
1 Selects VCO 2. The VCO frequency is scaled by a factor of 2 (low VCO Selects VCO 1 (high VCO frequency
frequency range).
range)
1 Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL
internal VCO output. MPC9773 is fully static and no minimum frequency limit enabled.
applies. All PLL related AC characteristics are not applicable.
INV_CLK
1 QC2 and QC3 are in phase with QC0 and QC1
QC2 and QC3 are inverted (180° phase
shift) with respect to QC0 and QC1
MR/OE
1 Outputs disabled (high-impedance state) and device is reset. During reset/ Outputs enabled (active)
output disable the PLL feedback loop is open and the internal VCO is tied to
its lowest frequency. The MPC9773 requires reset after any loss of PLL lock.
Loss of PLL lock may occur when the external feedback path is interrupted.
The length of the reset pulse should be greater than one reference clock
cycle (CCLKx). The device is reset by the internal power-on reset (POR)
circuitry during power-up.
MPC9773 REVISION 6 MARCH 16, 2016
3
©2016 Integrated Device Technology, Inc.







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