LED Driver. TPS92074D Datasheet

TPS92074D Driver. Datasheet pdf. Equivalent

TPS92074D Datasheet
Recommendation TPS92074D Datasheet
Part TPS92074D
Description Buck PFC LED Driver
Feature TPS92074D; TPS92074 www.ti.com SLUSBO7 – AUGUST 2013 Non-Isolated, Buck PFC LED Driver with Digital Referenc.
Manufacture etcTI
Datasheet
Download TPS92074D Datasheet




Texas Instruments TPS92074D
TPS92074
www.ti.com
SLUSBO7 – AUGUST 2013
Non-Isolated, Buck PFC LED Driver with Digital Reference Control
Check for Samples: TPS92074
FEATURES
1
• Controlled Reference Derived PFC
• Digital 50/60 Hz Synchronization
• Constant LED current operation
• Single Winding Magnetic Configurations
• Low Typical Operating Current
• Fast Start-up
• Overvoltage Protection
• Feedback Short-Circuit Protection
• Wide Temperature Operation Range
• Low BOM Cost and Small PCB Footprint
• Patent Pending Digital Architecture
• 8-Pin SOIC and 6-Pin TSOT Available
APPLICATIONS
• Non Phase Dimmable LED Lamps
• Bulb Replacement
• Area Lighting
DESCRIPTION
The TPS92074 is a hybrid power factor controller
(PFC) optimized for driving LED lighting solutions that
do not require phase dimming compatibility. The
device monitors the converter rectified AC waveform
using an internal, low-power, digital controller. The
controller and DAC generate a synchronized
triangular reference to regulate the output current. By
allowing for some variation in the LED current over a
line cycle and maintaining a regulated overall average
current, high power factor solutions can be achieved.
Using a constant off-time control, the solution
achieves low component count, high efficiency and
inherently provides variation in the switching
frequency. This variation creates an emulated spread
spectrum effect easing the converters EMI signature
and allowing a smaller input filter.
The TPS92074 also includes standard features:
current limit, overvoltage protection, thermal shut-
down, and VCC undervoltage lockout, all in packages
utilizing only 6 pins.
SIMPLIFIED APPLICATION DIAGRAM
EMI Filter
LED +
TPS92074
VSEN COFF
GND VCC
LED -
ISNS GATE
VIN
AC
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated



Texas Instruments TPS92074D
TPS92074
SLUSBO7 – AUGUST 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
All voltages are with respect to GND, –40°C < TJ = TA < 125°C, all currents are positive into and negative out of the specified
terminal (unless otherwise noted)
VALUE
MIN
MAX
UNIT
Input voltage range
VCC
–0.3
22
V
VSEN, COFF
–0.3
6.0
Bias and ISNS
IQ bias current (non-switching)
ISNS(2) to Ground
2.5 mA
–0.3
2.5
V
Gate
GATE - continuous
–0.3
18
V
GATE - 100 ns
–2.5
20.5
V
Continuous power dissipation
Internally Limited
Electrostatic discharge
Human Body Model (HBM)
2
kV
Field Induced Charged Device Model (FICDM)
Operating junction temperature, TJ(3)
Storage temperature range, Tstg
Lead temperature, soldering, 10s
750
V
160
°C
–65
150
°C
260
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) ISNS can sustain –2 V for 100 ns without damage.
(3) Maximum junction temperature is internally limited.
THERMAL INFORMATION
θJA
θJCtop
θJB
ψJT
ψJB
θJCbot
THERMAL METRIC(1)
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
TPS92074
SOIC
(D)
TSOT
(DDC)
8 PINS
6 PINS
112.3
165.5
58.4
28.8
52.5
24.6
12.5
0.3
51.9
23.8
NA
NA
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
2
Submit Documentation Feedback
Product Folder Links: TPS92074
Copyright © 2013, Texas Instruments Incorporated



Texas Instruments TPS92074D
TPS92074
www.ti.com
SLUSBO7 – AUGUST 2013
RECOMMENDED OPERATING CONDITIONS(1)
Unless otherwise noted, all voltages are with respect to GND, –40°C < TJ = TA < 125°C.
Supply input voltage range VCC
Operating junction temperature
MIN TYP MAX UNIT
11
18 V
–40
125 °C
(1) Operating Ratings are conditions under which operation of the device is specified and do not imply assured performance limits. For
specified performance limits and associated test conditions, see the Electrical Characteristics table.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified –40°C TJ = TA 125°C, VCC = 14 V, CVCC = 10 µF CGATE = 2.2 nF
PARAMETER
TEST CONDITIONS
MIN
SUPPLY VOLTAGE INPUT (VCC)
IQ
IQ_SD
VVCC
VVCC(OVP)
VVCC quiescent current
VVCC low power mode current
Input range
Overvoltage protection threshold
VVCC(UVLO) VVCC UVLO threshold
VVCC(HYS) VVCC UVLO hysteresis
LINE SYNCHRONIZATION
Not switching
VCC < VCC(UVLO)
VCC VCC(OVP)
VCC > VCC(OVP)
VCC rising
VCC falling
18.0
5.75
VSENTH-Hi VSEN line detect rising threshold
VSENTH-Low VSEN line detect falling threshold
OFF-TIME CONTROL
0.9
0.465
VCOFF
OFF capacitor threshold
RCOFF
OFF capacitor pull-down resistance
tOFF(max)
Maximum off-time
GATE DRIVER OUTPUT (GATE)
1.14
RGATE(H)
Gate sourcing resistance
RGATE(L)
Gate sinking resistance
CURRENT SENSE
VISNS
Average ISNS limit threshold
DAC: 63/127
445
VCL
Current limit
Leading edge blanking
tISNS
Current limit reset delay
ISNS limit to GATE delay
tCOFF_DLY OFF capacitor limit to GATE delay
THERMAL SHUTDOWN
TSD
THYS
Thermal limit threshold
Thermal limit hysteresis
TYP
1.3
120
9.8
6.40
3.3
1.0
0.500
1.20
33
280
3
3
500
1.2
240
280
33
33
160
20
MAX
2.5
250
18
20.0
10.5
1.1
0.540
1.285
60
8
8
555
UNIT
mA
µA
V
V
V
V
V
V
V
V
Ω
μs
Ω
Ω
mV
V
ns
µs
ns
ns
°C
°C
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS92074
Submit Documentation Feedback
3







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)