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PWM CONTROLLER. UTC3843E Datasheet |
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UTC3843D/E
LINEAR INTEGRATED CIRCUIT
CURRENT MODE PWM CONTROL
CIRCUITS
DESCRIPTION
The UTC3843D/E provides the necessary features to
implement off-line or DC to DC fixed frequency current mode
control schemes with a minimal external parts count. Internally
implemented circuits include under-voltage lockout featuring
start up current less than 1mA,a precision reference trimmed
for accuracy at the error amp input, logic to insure latched
operation, a PWM comparator which also provides current limit
control,and a totem pole output stage designed to source or
sink high peak current.The output stage, suitable for driving N
channel MOSFETs,is low in the off state.
DIP-8
FEATURES
*Optimized for off-line and DC to DC converts
*Low start up current(<1mA)
*Automatic feed forward compensation
*Pulse-by-Pulse current limiting
*Enhanced load response characteristics
*Under-voltage lockout with hysteresis
*Double pulse Suppression
*High current totem pole output
*Internally trimmed bandgap reference
*500kHz operation
*Low Ro error amp
SOP-8
ORDERING INFORMATION
Device
Package
UTC3248D
DIP-8-300-2.54
UTC3248E
SOP-8-225-1.27
BLOCK DIAGRAM
Vref
8
Internal
Bias
VFB
2
COMP 1
CURRENT SENSE 3
RT/CT 4
1/2Vref
ERROR
AMPLIFIER
5V REF
S/R
Vref
Good
Logic
1/3Vref
U.V.L.O
CURRENT
SENSE
COMPAREATOR
1V
R
PWM
LATCH
S
OSCILLATOR
7 Vcc
5 GND
7 Vcc
6 OUTPUT
5 GND
YOUWANG ELECTRONICS CO.LTD
1
2006.07.11
|
UTC3843D/E
LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS(Ta=25°C)
Characteristic
Symbol
Value
Unit
Supply Voltage(Low Impedence Source)
VCC
30
V
Supply Voltage(Icc<30mA)
Vcc
Self Limiting
V
Output Current
Io
±1
A
Output Energy(capacitive Load)
5
µJ
Analog Inputs(pin 2,3)
VI(ANA)
-0.3 to +6.3
V
Error Amplifier Output Sink Current
ISINK(EA)
10
mA
Power Dissipation
PD
at Tamb≤25°C 1.0
W
Lead Temperature
Tlead
300
°C
Storage Temperature
Tstg
-65~+150
°C
Note 1: Ta>25°C,PD derated with 8mW/°C.
ELECTRICAL CHARACTERISTICS
(0≤Ta≤70°C,VCC=15V,RT=10kΩ,CT=3.3nF,unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min Typ Max Units
Reference Section
Output Voltage
VREF Tj=25°C,Io=1mA
4.90 5.00 5.10 V
Line Regulation
∆VREF 12≤VIN≤25V
6
20 mV
Load Regulation
∆VREF 1≤Io=20mA
6
25 mV
Temp Dtability
(Note 2)
0.2 0.4 mV/°C
Total Output Variation
Line,Load,Temp(note 2)
4.82
5.18 µV
Output Noise Voltage
Vosc 10Hz≤f≤10kHz,Tj=25°C (note 2)
50
mV
Long term stability
Ta=25°C,1000Hrs(note 2)
5
25 mV
Output Short Circuit
ISC
-30 -100 -180 mA
Oscillator Section
Initial Accurcy
f
Tj=25°C
47
52
57 kHz
Voltage Stability
∆f/∆Vcc 12≤Vcc≤25V
0.2
1
%
Temp stability
Tmin≤TA≤Tmax(note 2)
5
%
Amplitude
Vosc Vpin 4 peak to peak
1.7
V
Error Amplifier Section
Input Voltage
VI(EA) Vpin 1=2.5V
2.42 2.50 2.58 V
Input Bias current
IBIAS
-0.3 -2
µA
AVOL
2 ≤Vo≤4V
60
90
dB
Unity Gain Bandwidth
Tj=25°C (note 2)
0.7
1
mHz
PSRR
I2≤Vcc≤25V
60
70
dB
Output Sink Current
Isink Vpin 2=2.7V,Vpin 1=1.1V
2
6
mA
Output Source Current
Isource Vpin 2=2.3V,Vpin 1=5V
-0.5 -0.8
mA
Vout High
VOH Vpin 2=2.3V, RL=15kΩ to GND
5
6
V
Vout Low
VOL Vpin 2=2.7V,Vpin 1=1.1V
0.7 1.1
V
Current Sense section
Gain
GV (note 3,4)
2.85
3
3.15 V/V
Maximum Input signal
VI(MAX) Vpin 1=5V( note 3)
0.9
1
1.1
V
PSRR
12≤Vcc≤25V
70
dB
Input Bias Current
IBIAS
-2
-10 µA
Delay to Output
Vpin 3=0 to 2V
150 300 ns
Output Section
Output low Level
VOL Isink=20mA
Isink=200mA
0.1 0.4
V
1.5 2.2
V
YOUWANG ELECTRONICS CO.LTD
2
2006.07.11
|
UTC3843D/E
LINEAR INTEGRATED CIRCUIT
(conitinued)
Characteristic
Output High Level
Rise Time
Fall Time
UVLO Saturation
Symbol
Test Conditions
VOH Isource=20mA
Isource=200mA
tR Tj=25°C,CL=1nF(note 2)
tF Tj=25°C,CL=1nF(note 2)
Vcc=5V,Isink=10mA
Under-Voltage Lockout Output Section
Start Threshold
VTH(ST)
Min.Operating Voltage After Turn VOPR(min)
On
PWM Section
Maximum duty Cycle
Minimum Duty Cycle
Total Standby Current
Start-up Current
Operating Supply Current
Vcc Zener Voltage
D(MAX)
D(MIN)
IST
ICC(opr) Vpin 2=Vpin 3=0V
Vz Icc=25mA
note 2:These parameters,although guaranteed ,are not 100% tested in production.
note 3:Parameters measured at trip point of latch with Vpin 2=0.
note 4:Gain defined as:
ǻVpin 1
A=
;0 Vpin 3 0.8V
ǻVpin 3
note 5:Adjust Vcc above the start threshold before setting at 15V.
OPEN-LOOP LABORATORY TEST CIRCUIT
RT
1
8
Error Amp
Adjust
2
7
3
6
5kȍ
4
5
CT
Min Typ Max Units
13 13.5
V
12 13.5
V
50 150 ns
50 150 ns
0.7 1.2
V
7.8 8.4 9.0
V
7.0 7.6 8.2
V
95
97 100
%
0
%
0.5
1
mA
11
17 mA
34
V
Vref
A
Vcc
1kȍ
/ 1W
OUTPUT
High peak current associated with capacitive loads
necessitate careful grounding techniques.Timing and
bypass capacitors should be connected close to pin 5 in
single point GND.The transistor and 5k¡ potentio -
meter are used to sample the oscillator waveform and
apply an adjustable Ramp to Pin 3.
YOUWANG ELECTRONICS CO.LTD
3
2006.07.11
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