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Quad UART. TL16CP754C Datasheet

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Quad UART. TL16CP754C Datasheet






TL16CP754C UART. Datasheet pdf. Equivalent




TL16CP754C UART. Datasheet pdf. Equivalent





Part

TL16CP754C

Description

Quad UART

Manufacture

Texas Instruments

Datasheet
Download TL16CP754C Datasheet


Texas Instruments TL16CP754C

TL16CP754C; TL16CP754C, TL16C754C www.ti.com SLLS6 44H – DECEMBER 2007 – REVISED JANUA RY 2014 TL16CP754C and TL16C754C – Q uad UARTs With 64-Byte FIFO Check for S amples: TL16CP754C, TL16C754C FEATURES 1 • ST16C654/654D Pin Compatible Wit h Additional Enhancements • Support u p to: – 24-MHz Crystal Input Clock (1 .5 Mbps) – 48-MHz Oscillator Input Cl ock (3 Mbps) for 5-V Operation –.


Texas Instruments TL16CP754C

32-MHz Oscillator Input Clock (2 Mbps) for 3.3-V Operation – 24-MHz Input Cl ock (1.5 Mbps) for 2.5-V Operation – 16-MHz Input Clock (1 Mbps) for 1.8-V O peration • 64-Byte Transmit FIFO • 64-Byte Receive FIFO With Error Flags Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DM A and Interrupt Generation • Programm able Receive FIFO Trigger Leve.


Texas Instruments TL16CP754C

ls for Software/Hardware Flow Control Software/Hardware Flow Control – Pr ogrammable Xon/Xoff Characters – Prog rammable Auto-RTS and Auto-CTS • Opti onal Data Flow Resume by Xon Any Charac ter • RS-485 Mode Support • Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply • Characterized for Operation From –40 °C to 85°C, Available in Commercial a nd Industrial Temperature Grades • S.



Part

TL16CP754C

Description

Quad UART

Manufacture

Texas Instruments

Datasheet
Download TL16CP754C Datasheet




 TL16CP754C
TL16CP754C, TL16C754C
www.ti.com
SLLS644H – DECEMBER 2007 – REVISED JANUARY 2014
TL16CP754C and TL16C754C – Quad UARTs With 64-Byte FIFO
Check for Samples: TL16CP754C, TL16C754C
FEATURES
1
• ST16C654/654D Pin Compatible With
Additional Enhancements
• Support up to:
– 24-MHz Crystal Input Clock (1.5 Mbps)
– 48-MHz Oscillator Input Clock (3 Mbps) for
5-V Operation
– 32-MHz Oscillator Input Clock (2 Mbps) for
3.3-V Operation
– 24-MHz Input Clock (1.5 Mbps) for 2.5-V
Operation
– 16-MHz Input Clock (1 Mbps) for 1.8-V
Operation
• 64-Byte Transmit FIFO
• 64-Byte Receive FIFO With Error Flags
• Programmable and Selectable Transmit and
Receive FIFO Trigger Levels for DMA and
Interrupt Generation
• Programmable Receive FIFO Trigger Levels for
Software/Hardware Flow Control
• Software/Hardware Flow Control
– Programmable Xon/Xoff Characters
– Programmable Auto-RTS and Auto-CTS
• Optional Data Flow Resume by Xon Any
Character
• RS-485 Mode Support
• Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply
• Characterized for Operation From –40°C to
85°C, Available in Commercial and Industrial
Temperature Grades
• Software-Selectable Baud-Rate Generator
• Prescaler Provides Additional Divide-by-4
Function
• Programmable Sleep Mode
• Programmable Serial Interface Characteristics
– 5-, 6-, 7-, or 8-Bit Characters
– Even, Odd, or No Parity Bit Generation and
Detection
– 1-, 1.5-, or 2-Stop Bit Generation
• False Start Bit Detection
• Complete Status Reporting Capabilities in
Both Normal and Sleep Mode
• Line Break Generation and Detection
• Internal Test and Loopback Capabilities
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and CD)
• Infrared Data Association (IrDA) Capability
DESCRIPTION
The '754C is a quad universal asynchronous receiver
transmitter (UART) with 64-byte FIFOs, automatic
hardware and software flow control, and data rates
up to 3 Mbps. It incorporates the functionality of four
UARTs, each UART having its own register set and
FIFOs. The four UARTs share only the data bus
interface and clock source, otherwise they operate
independently. Another name for the UART function
is Asynchronous Communications Element (ACE),
and these terms are used interchangeably. The bulk
of this document describes the behavior of each
ACE, with the understanding that four such devices
are incorporated into the '754C. The '754C offers
enhanced features. It has a transmission control
register (TCR) that stores received FIFO threshold
level to start or stop transmission during hardware
and software flow control. With the FIFO RDY
register, the software gets the status of
TXRDY/RXRDY for all four ports in one access. On-
chip status registers provide the user with error
indications, operational status, and modem interface
control. System interrupts may be tailored to meet
user requirements. An internal loopback capability
allows onboard diagnostics.
Each UART transmits data sent to it from the
peripheral 8-bit bus on the TX signal and receives
characters on the RX signal. Characters can be
programmed to be 5, 6, 7, or 8 bits. The UART has a
64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels.
The UART generates its own desired baud rate
based upon a programmable divisor and its input
clock. It can transmit even, odd, or no parity and 1-,
1.5-, or 2-stop bits. The receiver can detect break,
idle or framing errors, FIFO overflow, and parity
errors. The transmitter can detect FIFO underflow.
The UART also contains a software interface for
modem control operations, and software flow control
and hardware flow control capabilities.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2014, Texas Instruments Incorporated





 TL16CP754C
TL16CP754C, TL16C754C
SLLS644H – DECEMBER 2007 – REVISED JANUARY 2014
www.ti.com
DESCRIPTION (CONTINUED)
The '754C is available in a 64-pin TQFP PM package. RXRDY and TXRDY functionality is not supported in the
TL16C754CPM device.
TERMINAL
NAME
NO.
A0
24
A1
23
A2
22
CDA, CDB,
CDC, CDD
64, 18,
31, 49
CLKSEL
21
CSA, CSB,
CSC, CSD
7, 11,
38, 42
CTSA, CTSB,
CTSC, CTSD
2, 16,
33, 47
Table 1. Terminal Functions
I/O DESCRIPTION
I
Address bit 0 select. Internal registers address selection. Refer to Figure 22 for Register
Address Map.
I
Address bit 1 select. Internal registers address selection. Refer to Figure 22 for Register
Address Map.
I
Address bit 2 select. Internal registers address selection. Refer to Figure 22 for Register
Address Map.
Carrier detect (active low). These inputs are associated with individual UART channels A
I through D. A low on these pins indicates that a carrier has been detected by the modem for that
channel.
Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset,
a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler. A logic 0 (GND) on CLKSEL
I
selects the divide-by-4 prescaler. The value of CLKSEL is latched into MCR[7] at the trailing
edge of RESET. A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on
CLKSEL will latch a 1 into MCR[7]. MCR[7] can be changed after RESET to alter the prescaler
value.
Chip select A, B, C, and D (active low). These pins enable data transfers between the user
I CPU and the '754C for the channel or channels addressed. Individual UART sections (A, B, C,
D) are addressed by providing a low on the respective CSA through CSD pin.
Clear to send (active low). These inputs are associated with individual UART channels A
through D. A low on the CTS pins indicates the modem or data set is ready to accept transmit
I data from the '754C. Status can be checked by reading MSR[4]. These pins only affect the
transmit and receive operations when auto CTS function is enabled through the enhanced
feature register (EFR[7]), for hardware flow control operation.
2
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Copyright © 2007–2014, Texas Instruments Incorporated
Product Folder Links: TL16CP754C TL16C754C





 TL16CP754C
TL16CP754C, TL16C754C
www.ti.com
SLLS644H – DECEMBER 2007 – REVISED JANUARY 2014
Table 1. Terminal Functions (continued)
TERMINAL
NAME
NO.
D0–D2,
D3–D7
53–60
DSRA, DSRB,
DSRC, DSRD
1, 17,
32, 48
DTRA, DTRB,
DTRC, DTRD
3, 15,
34, 46
GND
INTA, INTB,
INTC, INTD
14, 28,
45, 61
6, 12,
37, 43
INTSEL
IOR
IOW
RESET
RIA, RIB,
RIC, RID
40
9
27
63, 19,
30, 50
RTSA, RTSB,
RTSC, RTSD
5, 13,
36, 44
RXA, RXB,
RXC, RXD
62, 20,
29, 51
RXRDY (1)
I/O DESCRIPTION
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to
I/O or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or
receive serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels A
I through D. A low on these pins indicates the modem or data set is powered on and is ready for
data exchange with the UART.
Data terminal ready (active low). These outputs are associated with individual UART channels
A through D. A low on these pins indicates that the '754C is powered on and ready. These pins
O
can be controlled through the modem control register. Writing a 1 to MCR[0] sets the DTR
output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR[0],
or after a reset. These pins can also be used in the RS-485 mode to control an external RS-485
driver or transceiver.
Pwr Power signal and power ground
Interrupt A, B, C, and D (active high). These pins provide individual channel interrupts, INTA-D.
INTAD are enabled when MCR[3] is set to a 1, interrupts are enabled in the interrupt enable
O register (IER) and when an interrupt condition exists. Interrupt conditions include: receiver
errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is
detected. INTAD are in the high-impedance state after reset.
Interrupt select (active high with internal pulldown). INTSEL can be used in conjunction with
MCR[3] to enable or disable the 3-state interrupts INTA-D or override MCR[3] and force
I continuous interrupts. Interrupt outputs are enabled continuously by making this pin a 1. Driving
this pin low allows MCR[3] to control the 3-state interrupt output. In this mode, MCR[3] is set to
a 1 to enable the 3-state outputs.
Read input (active low strobe). A valid low level on IOR loads the contents of an internal
I register defined by address bits A0 through A2 onto the '754C data bus (D0 through D7) for
access by an external CPU.
Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus
I (D0 through D7) from the external CPU to an internal register that is defined by address bits A0
through A2.
Reset. RESET resets the internal registers and all the outputs. The UART transmitter output
I and the receiver input are disabled during reset time. See '754C external reset conditions for
initialization details. RESET is an active high input.
Ring indicator (active low). These inputs are associated with individual UART channels A
I
through D. A low on these pins indicates the modem has received a ringing signal from the
telephone line. A low-to-high transition on these input pins generates a modem status interrupt,
if it is enabled.
Request to send (active low). These outputs are associated with individual UART channels A
through D. A low on the RTS pins indicates the transmitter has data ready and waiting to send.
O
Writing a 1 in the modem control register (MCR[1]) sets these pins to low, indicating data is
available. After a reset, these pins are set to 1. These pins only affect the transmit and receive
operation when auto-RTS function is enabled through the enhanced feature register (EFR[6]),
for hardware flow control operation.
Receive data input. These inputs are associated with individual serial channel data to the
'754C. During the local loopback mode, these RX input pins are disabled and TX data is
I internally connected to the UART RX input internally. During normal mode, RXn should be held
high when no data is being received. These outputs also can be used in IrDA mode. For more
information, see IrDA Overview.
Receive ready (active low). RXRDY contains the wire-ORed status of all four receive channel
O FIFOs, RXRDY A–D. It goes low when the trigger level has been reached or a timeout interrupt
occurs. It goes high when all RX FIFOs are empty and there is an error in RX FIFO.
(1) RXRDY and TXRDY functionality is not supported in the TL16C754CPM device.
Copyright © 2007–2014, Texas Instruments Incorporated
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