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DUAL UART. TL16C752C Datasheet

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DUAL UART. TL16C752C Datasheet






TL16C752C UART. Datasheet pdf. Equivalent




TL16C752C UART. Datasheet pdf. Equivalent





Part

TL16C752C

Description

DUAL UART



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity TL16C752C SLLS646C – MARCH 20 08 – REVISED JUNE 2017 TL16C752C Dual UART With 64-Byte FIFO 1 Features • 1 SC16C752B and XR16M752 Pin Compatible With Additional Enhancements • Suppo rt 1.8-V, 2.5-V, 3.3-V, or 5-V Supply Characterized for Operation from – 40°C to 85°C • Supports up to:.
Manufacture

Texas Instruments

Datasheet
Download TL16C752C Datasheet


Texas Instruments TL16C752C

TL16C752C; – 48-MHz Oscillator Input Clock (3 Mb ps) for 5-V Operation – 32-MHz Oscill ator Input Clock (2 Mbps) for 3.3-V Ope ration – 24-MHz Input Clock (1.5 Mbps ) for 2.5-V Operation – 16-MHz Input Clock (1 Mbps) for 1.8-V Operation • 64-Byte Transmit/Receive FIFO • Softw are-Selectable Baud-Rate Generator • Programmable and Selectable Transmit an d Receive FIFO Trigger Levels fo.


Texas Instruments TL16C752C

r DMA, Interrupt Generation, and Softwar e or Hardware Flow Control • Software /Hardware Flow Control – Programmable Xon and Xoff Characters With Optional Xon Any Character – Programmable Auto -RTS and Auto-CTS- Modem Control Functi ons (CTS, RTS, DSR, DTR, RI, and CD) DMA Signaling Capability for Both Rec eived and Transmitted Data on PN Packag e • RS-485 Mode Support • .


Texas Instruments TL16C752C

Infrared Data Association (IrDA) Capabil ity • Programmable Sleep Mode • Pro grammable Serial Interface Characterist ics – 5, 6, 7, or 8-Bit Characters Wi th 1, 1.5, or 2 Stop Bit Generation – Even, Odd, or No Parity Bit Generation and Detection • False Start Bit and Line Break Detection • Internal Test and Loopback Capabilities 2 Applicatio ns • GPS Systems • Ethernet Ne.

Part

TL16C752C

Description

DUAL UART



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity TL16C752C SLLS646C – MARCH 20 08 – REVISED JUNE 2017 TL16C752C Dual UART With 64-Byte FIFO 1 Features • 1 SC16C752B and XR16M752 Pin Compatible With Additional Enhancements • Suppo rt 1.8-V, 2.5-V, 3.3-V, or 5-V Supply Characterized for Operation from – 40°C to 85°C • Supports up to:.
Manufacture

Texas Instruments

Datasheet
Download TL16C752C Datasheet




 TL16C752C
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
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TL16C752C
SLLS646C – MARCH 2008 – REVISED JUNE 2017
TL16C752C Dual UART With 64-Byte FIFO
1 Features
1 SC16C752B and XR16M752 Pin Compatible With
Additional Enhancements
• Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply
• Characterized for Operation from –40°C to 85°C
• Supports up to:
– 48-MHz Oscillator Input Clock (3 Mbps) for 5-V
Operation
– 32-MHz Oscillator Input Clock (2 Mbps) for
3.3-V Operation
– 24-MHz Input Clock (1.5 Mbps) for 2.5-V
Operation
– 16-MHz Input Clock (1 Mbps) for 1.8-V
Operation
• 64-Byte Transmit/Receive FIFO
• Software-Selectable Baud-Rate Generator
• Programmable and Selectable Transmit and
Receive FIFO Trigger Levels for DMA, Interrupt
Generation, and Software or Hardware Flow
Control
• Software/Hardware Flow Control
– Programmable Xon and Xoff Characters With
Optional Xon Any Character
– Programmable Auto-RTS and Auto-CTS-
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and CD)
• DMA Signaling Capability for Both Received and
Transmitted Data on PN Package
• RS-485 Mode Support
• Infrared Data Association (IrDA) Capability
• Programmable Sleep Mode
• Programmable Serial Interface Characteristics
– 5, 6, 7, or 8-Bit Characters With 1, 1.5, or 2
Stop Bit Generation
– Even, Odd, or No Parity Bit Generation and
Detection
• False Start Bit and Line Break Detection
• Internal Test and Loopback Capabilities
2 Applications
• GPS Systems
• Ethernet Network Routers
• Infrared Transceivers
• Domestic Applications
• Portable Applications
• Factory Automation and Process Control
3 Description
The TL16C752C is a dual universal asynchronous
receiver transmitter (UART) with 64-byte FIFOs,
automatic hardware and software flow control, and
data rates up to 3 Mbps. The device offers enhanced
features. It has a transmission Character control
register (TCR) that stores received FIFO threshold
level to start or stop transmission during hardware
and software flow control.
Device Information(1)
PART NUMBER PACKAGE
BODY SIZE (NOM)
TL16C752C
TQFP (48)
VQFN (32)
7.00 mm × 7.00 mm
5.00 mm x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
A2 to A0
D7 to D0
CSA
CSB
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
RXRDYA
RXRDYB
RESET
XTAL1
XTAL2
Data Bus
Interface
Crystal
Oscillator
Buffer
UART Channel A
64-Byte TX FIFO TX
UART Regs
Baud
Rate
Generator
64-Byte RX FIFO
RX
UART Channel B
64-Byte TX FIFO TX
UART Regs
Baud
Rate
Generator
64-Byte RX FIFO
RX
TXA
CTSA
OPA, DTRA
DSRA, RIA, CDA
RTSA
RXA
TXB
CTSB
OPB, DTRB
DSRB, RIB, CDB
RTSB
RXB
VCC
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




 TL16C752C
TL16C752C
SLLS646C – MARCH 2008 – REVISED JUNE 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information .................................................. 9
7.5 Electrical Characteristics........................................... 9
7.6 Timing Requirements .............................................. 11
7.7 Typical Characteristics ............................................ 15
8 Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 28
8.5 Register Maps ......................................................... 30
9 Application and Implementation ........................ 46
9.1 Application Information............................................ 46
9.2 Typical Application .................................................. 46
10 Power Supply Recommendations ..................... 48
11 Layout................................................................... 49
11.1 Layout Guidelines ................................................. 49
11.2 Layout Example .................................................... 50
12 Device and Documentation Support ................. 51
12.1 Documentation Support ........................................ 51
12.2 Community Resource............................................ 51
12.3 Trademarks ........................................................... 51
12.4 Electrostatic Discharge Caution ............................ 51
12.5 Glossary ................................................................ 51
13 Mechanical, Packaging, and Orderable
Information ........................................................... 51
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2014) to Revision C
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Changed the Device Information table Body Size column From: 3.67 mm x 3.67 mm To: 7.00 mm x 7.00 mm ................. 1
• Corrected UART sections that are addressed with CSA and CSB in the Pin Functions table .............................................. 4
• Corrected the channel interrupt names for INTA and INTAB in the Pin Functions table ....................................................... 4
• Corrected UART channels for RTSA and RTSB in the Pin Functions table .......................................................................... 4
• Corrected UART sections that are addressed with CSA and CSB in the Pin Functions table .............................................. 6
• Corrected the channel interrupt names for INTA and INTAB in the Pin Functions table ....................................................... 7
• Corrected UART channels for RTSA and RTSB in the Pin Functions table .......................................................................... 7
• Combined Recommended Operating Conditions tables and updated min and max values for VI, VIH, and VIL .................... 8
• Changed the VCC low-level input voltage MAX value From: 0.3 x VCC To: 0.8 V in the Recommended Operating
Conditions table ...................................................................................................................................................................... 8
• Combined Electrical Characteristics tables ............................................................................................................................ 9
• Changed Test Conditions for ICC in the Electrical Characteristics VCC = 1.8 V table ............................................................. 9
• Changed the VOL MAX value From: 0.4 V To: 0.5 V in the Electrical Characteristics VCC = 5 V table ................................ 10
• Changed Figure 14 .............................................................................................................................................................. 17
• Changed (216-1) To: (216-1) in the Programmable Baud Rate Generator section ............................................................. 26
• Changed the FIFO RDY note in Figure 26 .......................................................................................................................... 30
• Deleted RX FIFO D status, RX FIFO C status, TX FIFO D status and TX FIFO C status from Address 111 in Table 7.... 30
• Changed table note (8) from "CS A-D" to "CS A-B"............................................................................................................. 32
• Changed BIT 3 in Table 11 from "IRQ(A-D)" to "IRQ(A-B)" ................................................................................................ 36
• Changed Figure 27 .............................................................................................................................................................. 42
2
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Copyright © 2008–2017, Texas Instruments Incorporated




 TL16C752C
www.ti.com
TL16C752C
SLLS646C – MARCH 2008 – REVISED JUNE 2017
Changes from Revision A (August 2009) to Revision B
Page
Thermal Information table....................................................................................................................................................... 9
• Replaced the register map table with Figure 26................................................................................................................... 30
• Updated Table 7 ................................................................................................................................................................... 31
5 Description (continued)
With the FIFO RDY register, the software gets the status of TXRDY or RXRDY for all two ports in one access.
On-chip status registers provide the user with error indications, operational status, and modem interface control.
System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard
diagnostics. The TL16C752C incorporates the functionality of two UARTs, each UART having its own register set
and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate
independently. Another name for the UART function is asynchronous communications element (ACE), and these
terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the
understanding that two such devices are incorporated into the TL16C752C device.
6 Pin Configuration and Functions
PFB Package
48-Pin TQFP
Top View
D5
1
D6
2
D7
3
RXB
4
RXA
5
TXRDYB
6
TXA
7
TXB
8
OPB
9
CSA
10
CSB
11
NC
12
NC – No internal connection
36
RESET
35
DTRB
34
DTRA
33
RTSA
32
OPA
31
RXRDYA
30
INTA
29
INTB
28
A0
27
A1
26
A2
25
NC
Not to scale
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: TL16C752C
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