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FLASH TECHNIQUE. TLC0820A Datasheet

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FLASH TECHNIQUE. TLC0820A Datasheet






TLC0820A TECHNIQUE. Datasheet pdf. Equivalent




TLC0820A TECHNIQUE. Datasheet pdf. Equivalent





Part

TLC0820A

Description

HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL CONVERTERS USING MODIFIED FLASH TECHNIQUE



Feature


TLC0820AC, TLC0820AI Advanced LinCMOS™ HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL CON VERTERS USING MODIFIED FLASH TECHNIQUES SLAS064A – SEPTEMBER 1986 – REVISE D JUNE 1994 D Advanced LinCMOS™ Sili con-Gate Technology D 8-Bit Resolution D Differential Reference Inputs D Paral lel Microprocessor Interface D Conversi on and Access Time Over Temperature Ran ge Read Mode . . . 2.5 µs .
Manufacture

Texas Instruments

Datasheet
Download TLC0820A Datasheet


Texas Instruments TLC0820A

TLC0820A; Max D No External Clock or Oscillator Co mponents Required D On-Chip Track and H old D Single 5-V Supply D TLC0820A Is D irect Replacement for National Semicond uctor ADC0820C/CC and Analog Devices AD 7820K/B/T DB, DW, OR N PACKAGE (TOP VI EW) ANLG IN 1 (LSB) D0 2 D1 3 D2 4 D3 5 WR/RDY 6 MODE 7 RD 8 INT 9 GND 10 20 VCC 19 NC 18 OFLW 17 D7 (MSB) 16 D6 15 D5 14 D4 13 CS 12.


Texas Instruments TLC0820A

REF + 11 REF – FN PACKAGE (TOP VIEW) description D1 D0 (LSB) ANLG IN VCC NC The TLC0820AC and the TLC0820AI are Advanced LinCMOS™ 8-bit analog-to-d igital converters each consisting of t wo 4-bit flash converters, a 4-bit digi tal-to-analog converter, a summing (err or) amplifier, control logic, and a res ult latch circuit. The modified flash t echnique allows low-po.


Texas Instruments TLC0820A

wer integrated circuitry to complete D2 D3 WR/RDY MODE 3 2 1 20 19 4 18 5 17 6 16 7 15 OFLW D7 (MSB) D6 D5 an 8-bit conversion in 1.18 µs over t emperature. The on-chip track-and-hold circuit has a 100-ns RD 8 14 D4 9 10 11 12 13 INT GND REF – REF+ CS sam ple window and allows these devices to convert continuous analog signals havi ng slew rates of up .

Part

TLC0820A

Description

HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL CONVERTERS USING MODIFIED FLASH TECHNIQUE



Feature


TLC0820AC, TLC0820AI Advanced LinCMOS™ HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL CON VERTERS USING MODIFIED FLASH TECHNIQUES SLAS064A – SEPTEMBER 1986 – REVISE D JUNE 1994 D Advanced LinCMOS™ Sili con-Gate Technology D 8-Bit Resolution D Differential Reference Inputs D Paral lel Microprocessor Interface D Conversi on and Access Time Over Temperature Ran ge Read Mode . . . 2.5 µs .
Manufacture

Texas Instruments

Datasheet
Download TLC0820A Datasheet




 TLC0820A
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
D Advanced LinCMOSSilicon-Gate
Technology
D 8-Bit Resolution
D Differential Reference Inputs
D Parallel Microprocessor Interface
D Conversion and Access Time Over
Temperature Range
Read Mode . . . 2.5 µs Max
D No External Clock or Oscillator
Components Required
D On-Chip Track and Hold
D Single 5-V Supply
D TLC0820A Is Direct Replacement for
National Semiconductor ADC0820C/CC and
Analog Devices AD7820K/B/T
DB, DW, OR N PACKAGE
(TOP VIEW)
ANLG IN 1
(LSB) D0 2
D1 3
D2 4
D3 5
WR/RDY 6
MODE 7
RD 8
INT 9
GND 10
20 VCC
19 NC
18 OFLW
17 D7 (MSB)
16 D6
15 D5
14 D4
13 CS
12 REF +
11 REF –
FN PACKAGE
(TOP VIEW)
description
The TLC0820AC and the TLC0820AI are
Advanced LinCMOS8-bit analog-to-digital
converters each consisting of two 4-bit flash
converters, a 4-bit digital-to-analog converter, a
summing (error) amplifier, control logic, and a
result latch circuit. The modified flash technique
allows low-power integrated circuitry to complete
D2
D3
WR/RDY
MODE
3 2 1 20 19
4
18
5
17
6
16
7
15
OFLW
D7 (MSB)
D6
D5
an 8-bit conversion in 1.18 µs over temperature.
The on-chip track-and-hold circuit has a 100-ns
RD 8
14 D4
9 10 11 12 13
sample window and allows these devices to
convert continuous analog signals having slew
rates of up to 100 mV/µs without external
sampling components. TTL-compatible 3-state
NC – No internal connection
output drivers and two modes of operation allow
interfacing to a variety of microprocessors. Detailed information on interfacing to most popular microprocessors
is readily available from the factory.
TA
0°C to 70°C
– 40°C to 85°C
TOTAL
UNADJUSTED
ERROR
± 1 LSB
± 1 LSB
AVAILABLE OPTIONS
PACKAGE
SSOP
(DB)
PLASTIC
SMALL OUTLINE
(DW)
PLASTIC
CHIP CARRIER
(FN)
TLC0820ACDB TLC0820ACDW
TLC0820ACFN
TLC0820AIDW
TLC0820AIFN
PLASTIC DIP
(N)
TLC0820ACN
TLC0820AIN
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1994, Texas Instruments Incorporated
2–1




 TLC0820A
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
functional block diagram
12
REF+
11
REF –
4-Bit Flash
Analog-to-Digital 4 4
Converter
(4 MSBs)
4
4-Bit
Digital-to-Analog
Converter
Output
Latch
and
3-State
Buffers
1
ANLG IN
Summing
Amplifier
–1
+1
4-Bit Flash
Analog-to-Digital
4
Converter
(4 LSBs)
18
OFLW
2
D0 (LSB)
3
D1
4
D2
5
D3
14
D4
15
D5
16
D6
17
D7 (MSB)
Digital
Outputs
7
MODE
6
WR/RDY
13
CS
8
RD
Timing
and
Control
9
INT
2–2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TLC0820A
TERMINAL
NAME NO.
ANLG IN
1
CS
13
D0
2
D1
3
D2
4
D3
5
D4
14
D5
15
D6
16
D7
17
GND
10
INT
9
MODE
7
NC
19
OFLW
18
RD
8
REF –
11
REF +
12
VCC
20
WR/RDY
6
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
Terminal Functions
I/O
DESCRIPTION
I Analog input
I Chip select. CS must be low in order for RD or WR to be recognized by the ADC.
O Digital, 3-state output data, bit 1 (LSB)
O Digital, 3-state output data, bit 2
O Digital, 3-state output data, bit 3
O Digital, 3-state output data, bit 4
O Digital, 3-state output data, bit 5
O Digital, 3-state output data, bit 6
O Digital, 3-state output data, bit 7
O Digital, 3-state output data, bit 8 (MSB)
Ground
O Interrupt. In the write-read mode, the interrupt output (INT) going low indicates that the internal count-down delay
time, td(int), is complete and the data result is in the output latch. The delay time td(int) is typically 800 ns starting
after the rising edge of WR (see operating characteristics and Figure 3). If RD goes low prior to the end of td(int),
INT goes low at the end of td(RIL) and the conversion results are available sooner (see Figure 2). INT is reset by
the rising edge of either RD or CS.
I Mode select. MODE is internally tied to GND through a 50-µA current source, which acts like a pulldown resistor.
When MODE is low, the read mode is selected. When MODE is high, the write-read mode is selected.
No internal connection
O Overflow. Normally OFLW is a logical high. However, if the analog input is higher than Vref+, OFLW will be low at
the end of conversion. It can be used to cascade two or more devices to improve resolution (9 or 10 bits).
I Read. In the write-read mode with CS low, the 3-state data outputs D0 through D7 are activated when RD goes
low. RD can also be used to increase the conversion speed by reading data prior to the end of the internal
count-down delay time. As a result, the data transferred to the output latch is latched after the falling edge of RD.
In the read mode with CS low, the conversion starts with RD going low. RD also enables the 3-state data outputs
on completion of the conversion. RDY going into the high-impedance state and INT going low indicate completion
of the conversion.
I Reference voltage. REF – is placed on the bottom of the resistor ladder.
I Reference voltage. REF + is placed on the top of the resistor ladder.
Power supply voltage
I/O Write ready. In the write-read mode with CS low, the conversion is started on the falling edge of the WR input signal.
The result of the conversion is strobed into the output latch after the internal count-down delay time, td(int), provided
that the RD input does not go low prior to this time. The delay time td(int) is approximately 800 ns. In the read mode,
RDY (an open-drain output) goes low after the falling edge of CS and goes into the high-impedance state when
the conversion is strobed into the output latch. It is used to simplify the interface to a microprocessor system.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2–3






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