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ANALOG-TO-DIGITAL CONVERTER. TLC0832 Datasheet

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ANALOG-TO-DIGITAL CONVERTER. TLC0832 Datasheet






TLC0832 CONVERTER. Datasheet pdf. Equivalent




TLC0832 CONVERTER. Datasheet pdf. Equivalent





Part

TLC0832

Description

8-BIT ANALOG-TO-DIGITAL CONVERTER



Feature


TLC0831C, TLC0831I TLC0832C, TLC0832I 8- BIT ANALOG-TO-DIGITAL CONVERTERS WITH S ERIAL CONTROL SLAS107B – JANUARY 1995 – REVISED APRIL 1996 D 8-Bit Resolu tion D Easy Microprocessor Interface or Standalone Operation D Operates Ratiom etrically or With 5-V Reference D Singl e Channel or Multiplexed Twin Channels With Single-Ended or Differential Input Options D Input Range.
Manufacture

Texas Instruments

Datasheet
Download TLC0832 Datasheet


Texas Instruments TLC0832

TLC0832; 0 to 5 V With Single 5-V Supply D Input s and Outputs Are Compatible With TTL a nd MOS D Conversion Time of 32 µs at f clock = 250 kHz D Designed to Be Interc hangeable With National Semiconductor A DC0831 and ADC0832 D Total Unadjusted E rror . . . ± 1 LSB TLC0831 . . . D OR P PACKAGE (TOP VIEW) CS 1 IN+ 2 IN– 3 GND 4 8 VCC 7 CLK 6 DO 5 REF TLC08 32 . . . D OR P PACKAG.


Texas Instruments TLC0832

E (TOP VIEW) CS 1 CH0 2 CH1 3 GND 4 8 VCC /REF 7 CLK 6 DO 5 DI description T hese devices are 8-bit successive-appro ximation analog-to-digital converters. The TLC0831 has single input channels; the TLC0832 has multiplexed twin input channels. The serial output is configur ed to interface with standard shift reg isters or microprocessors. The TLC0832 multiplexer is sof.


Texas Instruments TLC0832

tware configured for single-ended or dif ferential inputs. The differential anal og voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog v oltage span to the full 8 bits of resol ution. The operation of the TLC0831 and TLC0832 devices i.

Part

TLC0832

Description

8-BIT ANALOG-TO-DIGITAL CONVERTER



Feature


TLC0831C, TLC0831I TLC0832C, TLC0832I 8- BIT ANALOG-TO-DIGITAL CONVERTERS WITH S ERIAL CONTROL SLAS107B – JANUARY 1995 – REVISED APRIL 1996 D 8-Bit Resolu tion D Easy Microprocessor Interface or Standalone Operation D Operates Ratiom etrically or With 5-V Reference D Singl e Channel or Multiplexed Twin Channels With Single-Ended or Differential Input Options D Input Range.
Manufacture

Texas Instruments

Datasheet
Download TLC0832 Datasheet




 TLC0832
TLC0831C, TLC0831I
TLC0832C, TLC0832I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B – JANUARY 1995 – REVISED APRIL 1996
D 8-Bit Resolution
D Easy Microprocessor Interface or
Standalone Operation
D Operates Ratiometrically or With 5-V
Reference
D Single Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
D Input Range 0 to 5 V With Single 5-V Supply
D Inputs and Outputs Are Compatible With
TTL and MOS
D Conversion Time of 32 µs at
fclock = 250 kHz
D Designed to Be Interchangeable With
National Semiconductor ADC0831 and
ADC0832
D Total Unadjusted Error . . . ± 1 LSB
TLC0831 . . . D OR P PACKAGE
(TOP VIEW)
CS 1
IN+ 2
IN– 3
GND 4
8 VCC
7 CLK
6 DO
5 REF
TLC0832 . . . D OR P PACKAGE
(TOP VIEW)
CS 1
CH0 2
CH1 3
GND 4
8 VCC /REF
7 CLK
6 DO
5 DI
description
These devices are 8-bit successive-approximation analog-to-digital converters. The TLC0831 has single input
channels; the TLC0832 has multiplexed twin input channels. The serial output is configured to interface with
standard shift registers or microprocessors.
The TLC0832 multiplexer is software configured for single-ended or differential inputs. The differential analog
voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the
voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of
resolution.
The operation of the TLC0831 and TLC0832 devices is very similar to the more complex TLC0834 and TLC0838
devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input
signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to VCC (done
internally on the TLC0832).
The TLC0831C and TLC0832C are characterized for operation from 0°C to 70°C. The TLC0831I and TLC0832I
are characterized for operation from – 40°C to 85°C.
TA
0°C to 70°C
– 40°C to 85°C
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
TLC0831CD
TLC0832CD
TLC0831CP
TLC0832CP
TLC0831ID
TLC0832ID
TLC0831IP
TLC0832IP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
1




 TLC0832
TLC0831C, TLC0831I
TLC0832C, TLC0832I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B – JANUARY 1995 – REVISED APRIL 1996
functional block diagram
CLK
CS
DI
(TLC0832
only)
Shift Register
D
ODD/EVEN
CLK Start
Start
Flip-Flop
CLK
S
R
To Internal
Circuits
SGL/DIF
CH0/IN+
CH1/IN –
Analog
MUX
EN
Comparator
Time
Delay
REF
(TLC0831
only)
EN
Ladder
and
Decoder
CS
CS
Bits 0–7
EN R
SAR
Logic
and
Latch
Bits 0–7
Bit 1
CLK R
9-Bit
Shift
Register
EOC
One
Shot
MSB
First
LSB
First
CLK
S
R
CS
CS
R
CLK
D
CS
DO
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TLC0832
TLC0831C, TLC0831I
TLC0832C, TLC0832I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B – JANUARY 1995 – REVISED APRIL 1996
functional description
The TLC0831 and TLC0832 use a sample-data-comparator structure that converts differential analog inputs
by a successive-approximation routine. The input voltage to be converted is applied to an input terminal and
is compared to ground (single ended), or to an adjacent input (differential). The TLC0832 input terminals can
be assigned a positive (+) or negative (–) polarity. The TLC0831 contains only one differential input channel with
fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,
between IN+ and IN–, to the TLC0831 or can be applied to IN+ with IN– grounded as a single ended input. When
the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the
converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. An interval of one clock period is
automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance
state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares
successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates
whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,
conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock
periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the
output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low
transition followed by address information.
A TLC0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift
register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the
TLC0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are
shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,
the input channel is selected and conversion starts. The TLC0832 DI terminal to the multiplexer shift register
is disabled for the duration of the conversion.
The TLC0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO
terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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