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Digital-to-Analog Converter. TLV5620CD Datasheet

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Digital-to-Analog Converter. TLV5620CD Datasheet






TLV5620CD Converter. Datasheet pdf. Equivalent




TLV5620CD Converter. Datasheet pdf. Equivalent





Part

TLV5620CD

Description

Quadruple 8-Bit Digital-to-Analog Converter

Manufacture

Texas Instruments

Datasheet
Download TLV5620CD Datasheet


Texas Instruments TLV5620CD

TLV5620CD; TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGIT AL-TO-ANALOG CONVERTERS D Four 8-Bit V oltage Output DACs D 3-V Single-Supply Operation D Serial Interface D High-Imp edance Reference Inputs D Programmable for 1 or 2 Times Output Range D Simulta neous Update Facility D Internal Power- On Reset D Low-Power Consumption D Half -Buffered Output SLAS110B – JANUARY 1995 – REVISED APRIL.


Texas Instruments TLV5620CD

1997 D OR N PACKAGE (TOP VIEW) GND 1 R EFA 2 REFB 3 REFC 4 REFD 5 DATA 6 CLK 7 14 VDD 13 LDAC 12 DACA 11 DACB 10 DAC C 9 DACD 8 LOAD applications D Program mable Voltage Sources D Digitally Contr olled Amplifiers/Attenuators D Mobile C ommunications D Automatic Test Equipmen t D Process Monitoring and Control D Si gnal Synthesis description The TLV5620C and TLV5620I are .


Texas Instruments TLV5620CD

quadruple 8-bit voltage output digital-t o-analog converters (DACs) with buffere d reference inputs (high impedance). Th e DACs produce an output voltage that r anges between either one or two times t he reference voltages and GND; and, the DACs are monotonic. The device is simp le to use, because it runs from a singl e supply of 3 V to 3.6 V. A power-on re set function is in.



Part

TLV5620CD

Description

Quadruple 8-Bit Digital-to-Analog Converter

Manufacture

Texas Instruments

Datasheet
Download TLV5620CD Datasheet




 TLV5620CD
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
D Four 8-Bit Voltage Output DACs
D 3-V Single-Supply Operation
D Serial Interface
D High-Impedance Reference Inputs
D Programmable for 1 or 2 Times Output
Range
D Simultaneous Update Facility
D Internal Power-On Reset
D Low-Power Consumption
D Half-Buffered Output
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
D OR N PACKAGE
(TOP VIEW)
GND 1
REFA 2
REFB 3
REFC 4
REFD 5
DATA 6
CLK 7
14 VDD
13 LDAC
12 DACA
11 DACB
10 DACC
9 DACD
8 LOAD
applications
D Programmable Voltage Sources
D Digitally Controlled Amplifiers/Attenuators
D Mobile Communications
D Automatic Test Equipment
D Process Monitoring and Control
D Signal Synthesis
description
The TLV5620C and TLV5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with
buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either
one or two times the reference voltages and GND; and, the DACs are monotonic. The device is simple to use,
because it runs from a single supply of 3 V to 3.6 V. A power-on reset function is incorporated to ensure
repeatable start-up conditions.
Digital control of the TLV5620C and TLV5620I is over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word
comprises eight bits of data, two DAC select bits, and a range bit, the latter allowing selection between the times
1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be
written to the device, then all DAC outputs update simultaneously through control of LDAC. The digital inputs
feature Schmitt triggers for high noise immunity.
The 14-terminal small-outline (SO) package allows digital control of analog functions in space-critical
applications. The TLV5620C is characterized for operation from 0°C to 70°C. The TLV5620I is characterized
for operation from – 40°C to 85°C. The TLV5620C and TLV5620I do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D)
0°C to 70°C
TLV5620CD
– 40°C to 85°C
TLV5620ID
PLASTIC DIP
(N)
TLV5620CN
TLV5620IN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1997, Texas Instruments Incorporated
1





 TLV5620CD
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
functional block diagram
REFA 2 +
REFB 3 +
REFC 4 +
REFD 5 +
8 Latch
8 Latch
8 Latch
8 Latch
DAC
Latch
8
×2
DAC
Latch
8
×2
DAC
Latch
8
×2
DAC
Latch
8
×2
CLK 7
DATA 6
LOAD 8
Serial
Interface
13
LDAC
Power-On
Reset
+
12
DACA
+
11 DACB
+
10
DACC
+
9
DACD
Terminal Functions
TERMINAL
NAME NO.
CLK
7
DACA
12
DACB
11
DACC
10
DACD
9
DATA
6
GND
1
LDAC
13
LOAD
8
REFA
2
REFB
3
REFC
4
REFD
5
VDD
14
I/O
DESCRIPTION
I Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock
applied to the CLK terminal.
O DAC A analog output
O DAC B analog output
O DAC C analog output
O DAC D analog output
I Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.
Each data bit is clocked into the register on the falling edge of the clock signal.
I Ground return and reference terminal
I Load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial
interface. The DAC outputs are only updated when LDAC is taken from high to low.
I Serial interface load control. When the LDAC terminal is low, the falling edge of the LOAD signal latches the digital
data into the output latch and immediately produces the analog voltage at the DAC output terminal.
I Reference voltage input to DAC A. This voltage defines the output analog range.
I Reference voltage input to DAC B. This voltage defines the analog output range.
I Reference voltage input to DAC C. This voltage defines the analog output range.
I Reference voltage input to DAC D. This voltage defines the analog output range.
I Positive supply voltage
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265





 TLV5620CD
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
detailed description
The TLV5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance
of the output buffer. Since the inputs are buffered, the DACs always presents a high-impedance load to the
reference source.
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.
On power up, the DACs are reset to CODE 0.
Each output voltage is given by:
+ VO(DACA|B|C|D)
REF
CODE
256
) (1 RNG bit value)
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.
Table 1. Ideal Output Transfer
D7 D6 D5 D4 D3 D2 D1 D0
00000000
00000001
01111111
10000000
11111111
OUTPUT VOLTAGE
GND
(1/256) × REF (1+RNG)
(127/256) × REF (1+RNG)
(128/256) × REF (1+RNG)
(255/256) × REF (1+RNG)
data interface
With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have
been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as
shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When
LDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data
transfers using two 8-clock-cycle periods are shown in Figures 3 and 4.
Table 2 lists the A1 and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
Table 2. Serial Input Decode
A1
A0
0
0
0
1
1
0
1
1
DAC UPDATED
DACA
DACB
DACC
DACD
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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