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D-A Converter. TLV5618A-EP Datasheet

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D-A Converter. TLV5618A-EP Datasheet






TLV5618A-EP Converter. Datasheet pdf. Equivalent




TLV5618A-EP Converter. Datasheet pdf. Equivalent





Part

TLV5618A-EP

Description

Low-Power Dual 12-Bit D-A Converter

Manufacture

Texas Instruments

Datasheet
Download TLV5618A-EP Datasheet


Texas Instruments TLV5618A-EP

TLV5618A-EP; TLV5618AĆEP 2.7ĆV TO 5.5ĆV LOWĆPOWER DUAL 12ĆBIT DIGITALĆTOĆANALOG CONVE RTER WITH POWER DOWN SGLS214 − OCTOBE R 2003 features D Controlled Baseline − One Assembly/Test Site, One Fabrica tion Site D Extended Temperature Perfor mance of −55°C to 125°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Noti fication D Qualification Pedigree.


Texas Instruments TLV5618A-EP

† D Dual 12-Bit Voltage Output DAC D P rogrammable Settling Time − 3 µs in Fast Mode − 10 µs in Slow Mode † C omponent qualification in accordance wi th JEDEC and industry standards to ensu re reliable operation over an extended temperature range. This includes, but i s not limited to, Highly Accelerated St ress Test (HAST) or biased 85/85, tempe rature cycle, autoclave or u.


Texas Instruments TLV5618A-EP

nbiased HAST, electromigration, bond int ermetallic life, and mold compound life . Such qualification testing should not be viewed as justifying use of this co mponent beyond specified performance an d environmental limits. D Compatible W ith TMS320 and SPI Serial Ports D Diffe rential Nonlinearity <0.5 LSB Typ D Mon otonic Over Temperature D Direct Replac ement for TLC5618A.



Part

TLV5618A-EP

Description

Low-Power Dual 12-Bit D-A Converter

Manufacture

Texas Instruments

Datasheet
Download TLV5618A-EP Datasheet




 TLV5618A-EP
TLV5618AĆEP
2.7ĆV TO 5.5ĆV LOWĆPOWER DUAL 12ĆBIT
DIGITALĆTOĆANALOG CONVERTER WITH POWER DOWN
SGLS214 − OCTOBER 2003
features
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−55°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D Dual 12-Bit Voltage Output DAC
D Programmable Settling Time
− 3 µs in Fast Mode
− 10 µs in Slow Mode
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D Compatible With TMS320 and SPI Serial
Ports
D Differential Nonlinearity <0.5 LSB Typ
D Monotonic Over Temperature
D Direct Replacement for TLC5618A
applications
D Digital Servo Control Loops
D Digital Offset and Gain Adjustment
D Industrial Process Control
D Machine and Motion Control Devices
D Mass Storage Devices
D PACKAGE
(TOP VIEW)
DIN 1
SCLK 2
CS 3
OUTA 4
8 VDD
7 OUTB
6 REF
5 AGND
description
The TLV5618A is a dual 12-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface is
compatible with TMS320, SPI, QSPI, and Microwireserial ports. It is programmed with a 16-bit serial string
containing 4 control and 12 data bits.
The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a
Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC
allows the designer to optimize speed versus power dissipation.
Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It
is available in an 8-pin SOIC package.
The TLV5618AM is characterized for operation from − 55°C to 125°C.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−55°C to 125°C SOIC (D)
Tape and reel TLV5618AMDREP
5618ME
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2003 Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1





 TLV5618A-EP
TLV5618AĆEP
2.7ĆV TO 5.5ĆV LOWĆPOWER DUAL 12ĆBIT
DIGITALĆTOĆANALOG CONVERTER WITH POWER DOWN
SGLS214 − OCTOBER 2003
functional block diagram
REF AGND VDD
Power-On
Reset
Power and
Speed Control
2
DIN
SCLK
CS
Serial
Interface
12
and
Control
12
12-Bit
12
DAC A
Latch
Buffer
12
12
12-Bit
DAC B
Latch
x2
OUTA
x2
OUTB
TERMINAL
NAME
NO.
AGND
5
CS
3
DIN
1
OUTA
4
OUTB
7
REF
6
SCLK
2
VDD
8
Terminal Functions
I/O/P
DESCRIPTION
P Ground
I Chip select. Digital input active low, used to enable/disable inputs.
I Digital serial data input
O DAC A analog voltage output
O DAC B analog voltage output
I Analog reference voltage input
I Digital serial clock input
P Positive power supply
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265





 TLV5618A-EP
TLV5618AĆEP
2.7ĆV TO 5.5ĆV LOWĆPOWER DUAL 12ĆBIT
DIGITALĆTOĆANALOG CONVERTER WITH POWER DOWN
SGLS214 − OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Operating free-air temperature range, TA: TLV5618AM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Package thermal impedance, RθJA: D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131°C/W
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Long term high−temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall
device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
recommended operating conditions
MIN NOM
MAX
Supply voltage, VDD
Power on reset
VDD = 5 V
VDD = 3 V
4.5
5
5.5
2.7
3
3.3
0.55
2
VDD = 2.7 V
2
High-level digital input voltage, VIH
VDD = 5.5 V
2.4
VDD = 2.7 V
0.6
Low-level digital input voltage, VIL
VDD = 5.5 V
1
Reference voltage, Vref to REF terminal
VDD = 5 V (see Note 1)
VDD = 3 V (see Note 1)
AGND 2.048 VDD −1.5
AGND 1.024 VDD −1.5
Load resistance, RL
2
Load capacitance, CL
100
Clock frequency, f(CLK)
20
Operating free-air temperature, TA
TLV5618AM
− 55
125
NOTE 1: Due to the x2 output buffer, a reference input voltage (VDD−0.4 V)/2 causes clipping of the transfer function.
UNIT
V
V
V
V
V
k
pF
MHz
°C
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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