DatasheetsPDF.com

Buffer Gate. SN74AUC1G125-EP Datasheet

DatasheetsPDF.com

Buffer Gate. SN74AUC1G125-EP Datasheet






SN74AUC1G125-EP Gate. Datasheet pdf. Equivalent




SN74AUC1G125-EP Gate. Datasheet pdf. Equivalent





Part

SN74AUC1G125-EP

Description

Single Bus Buffer Gate



Feature


www.ti.com SN74AUC1G125-EP SINGLE BUS B UFFER GATE WITH 3-STATE OUTPUT SCES670 – MARCH 2007 FEATURES • Controlle d Baseline – One Assembly Site – On e Test Site – One Fabrication Site Extended Temperature Performance of 55°C to 125°C • Enhanced Diminish ing Manufacturing Sources (DMS) Support • Enhanced Product-Change Notificati on • Qualification Pedigree (1) • Opti.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G125-EP Datasheet


Texas Instruments SN74AUC1G125-EP

SN74AUC1G125-EP; mized for 1.8-V Operation and Is 3.6-V I /O Tolerant to Support Mixed-Mode Signa l Operation (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. Thi s includes, but is not limited to, High ly Accelerated Stress Test (HAST) or bi ased 85/85, temperature cycle, autoclav e or unbiased HAST.


Texas Instruments SN74AUC1G125-EP

, electromigration, bond intermetallic l ife, and mold compound life. Such quali fication testing should not be viewed a s justifying use of this component beyo nd specified performance and environmen tal limits. • Ioff Supports Partial- Power-Down Mode Operation • Sub-1-V O perable • Max tpd of 2.5 ns at 1.8 V • Low Power Consumption, 10-µA Max I CC • ±8-mA Output Drive at .


Texas Instruments SN74AUC1G125-EP

1.8 V • Latch-Up Performance Exceeds 1 00 mA Per JESD 78, Class II • ESD Pro tection Exceeds JESD 22 – 2000-V Huma n-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Devi ce Model (C101) DCK PACKAGE (TOP VIEW) OE 1 5 VCC A 2 GND 3 4Y See mechanical drawings for dimensions. DES CRIPTION/ORDERING INFORMATION The SN74A UC1G125 is operational at 0..

Part

SN74AUC1G125-EP

Description

Single Bus Buffer Gate



Feature


www.ti.com SN74AUC1G125-EP SINGLE BUS B UFFER GATE WITH 3-STATE OUTPUT SCES670 – MARCH 2007 FEATURES • Controlle d Baseline – One Assembly Site – On e Test Site – One Fabrication Site Extended Temperature Performance of 55°C to 125°C • Enhanced Diminish ing Manufacturing Sources (DMS) Support • Enhanced Product-Change Notificati on • Qualification Pedigree (1) • Opti.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G125-EP Datasheet




 SN74AUC1G125-EP
www.ti.com
SN74AUC1G125-EP
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES670 – MARCH 2007
FEATURES
Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCK PACKAGE
(TOP VIEW)
OE
1
5
VCC
A
2
GND
3
4Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The SN74AUC1G125 is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC1G125 is a single-line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated




 SN74AUC1G125-EP
SN74AUC1G125-EP
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES670 – MARCH 2007
ORDERING INFORMATION(1)
www.ti.com
TA
PACKAGE (2)
–55°C to 125°C SOT (SC-70) – DCK
Reel of 3000
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
CAUC1G125MDCKREP
UM_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(3) The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUTS
OE
A
L
H
L
L
H
X
OUTPUT
Y
H
L
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OE
2
A
4
Y
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0 V
IOK
Output clamp current
VO < 0 V
IO
Continuous output current
Continuous current through VCC or GND
θJA
Package thermal impedance(3)
Tstg
Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 VCC + 0.5
–50
–50
±20
±100
252
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
MIN
0.8
VCC
0.65 × VCC
1.7
MAX UNIT
2.7 V
V
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
Submit Documentation Feedback




 SN74AUC1G125-EP
www.ti.com
Recommended Operating Conditions (continued)
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
t/v Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
SN74AUC1G125-EP
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES670 – MARCH 2007
MIN
MAX UNIT
0
0.35 × VCC V
0.7
0
3.6 V
0
VCC
V
–0.7
–3
–5 mA
–8
–9
0.7
3
5 mA
8
9
20
10 ns/V
3
–55
125 °C
Submit Documentation Feedback
3



Recommended third-party SN74AUC1G125-EP Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)