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D-TYPE FLIP-FLOP. SN74AUCH16374 Datasheet

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D-TYPE FLIP-FLOP. SN74AUCH16374 Datasheet






SN74AUCH16374 FLIP-FLOP. Datasheet pdf. Equivalent




SN74AUCH16374 FLIP-FLOP. Datasheet pdf. Equivalent





Part

SN74AUCH16374

Description

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP



Feature


SN74AUCH16374 www.ti.com SCES404E – JULY 2002 – REVISED JULY 2012 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3 -STATE OUTPUTS Check for Samples: SN74A UCH16374 FEATURES 1 •2 Member of the Texas Instruments Widebus™ Family Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mod e Signal Operation • Ioff Supports Pa rtial-Power-Down Mode Operatio.
Manufacture

Texas Instruments

Datasheet
Download SN74AUCH16374 Datasheet


Texas Instruments SN74AUCH16374

SN74AUCH16374; n • Sub-1-V Operable • Max tpd of 2. 8 ns at 1.8 V • Low Power Consumption , 20 μA Max ICC • ±8-mA Output Driv e at 1.8 V • Bus Hold on Data Inputs Eliminates the Need for External Pullup /Pulldown Resistors • Latch-Up Perfor mance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) – 1000-.


Texas Instruments SN74AUCH16374

V Charged-Device Model (C101) DESCRIPTIO N/ORDERING INFORMATION This 16-bit edge -triggered D-type flip-flop is operatio nal at 0.8-V to 2.7-V VCC, but is desig ned specifically for 1.65-V to 1.95-V V CC operation. DGG OR DGV PACKAGE (TOP VIEW) 1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q 4 6 VCC 7 1Q5 8 1Q6 9 GND 10 1Q7 11 1Q8 12 2Q1 13 2Q2 14 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 .


Texas Instruments SN74AUCH16374

20 GND 21 2Q7 22 2Q8 23 2OE 24 48 1CLK 47 1D1 46 1D2 45 GND 44 1D3 43 1D4 42 V CC 41 1D5 40 1D6 39 GND 38 1D7 37 1D8 3 6 2D1 35 2D2 34 GND 33 2D3 32 2D4 31 VC C 30 2D5 29 2D6 28 GND 27 2D7 26 2D8 25 2CLK The SN74AUCH16374 is particularl y suitable for implementing buffer regi sters, I/O ports, bidirectional bus dri vers, and working registers. It can be used as two 8-bit .

Part

SN74AUCH16374

Description

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP



Feature


SN74AUCH16374 www.ti.com SCES404E – JULY 2002 – REVISED JULY 2012 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3 -STATE OUTPUTS Check for Samples: SN74A UCH16374 FEATURES 1 •2 Member of the Texas Instruments Widebus™ Family Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mod e Signal Operation • Ioff Supports Pa rtial-Power-Down Mode Operatio.
Manufacture

Texas Instruments

Datasheet
Download SN74AUCH16374 Datasheet




 SN74AUCH16374
SN74AUCH16374
www.ti.com
SCES404E – JULY 2002 – REVISED JULY 2012
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
Check for Samples: SN74AUCH16374
FEATURES
1
2 Member of the Texas Instruments Widebus™
Family
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
• Ioff Supports Partial-Power-Down Mode
Operation
• Sub-1-V Operable
• Max tpd of 2.8 ns at 1.8 V
• Low Power Consumption, 20 μA Max ICC
• ±8-mA Output Drive at 1.8 V
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 16-bit edge-triggered D-type flip-flop is
operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
DGG OR DGV PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
VCC 7
1Q5 8
1Q6 9
GND 10
1Q7 11
1Q8 12
2Q1 13
2Q2 14
GND 15
2Q3 16
2Q4 17
VCC 18
2Q5 19
2Q6 20
GND 21
2Q7 22
2Q8 23
2OE 24
48 1CLK
47 1D1
46 1D2
45 GND
44 1D3
43 1D4
42 VCC
41 1D5
40 1D6
39 GND
38 1D7
37 1D8
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
31 VCC
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2CLK
The SN74AUCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive
transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2012, Texas Instruments Incorporated




 SN74AUCH16374
SN74AUCH16374
SCES404E – JULY 2002 – REVISED JULY 2012
www.ti.com
TA
–40°C to 85°C
TSSOP – DGG
TVSOP – DGV
VFBGA – GQL
VFBGA – ZQL
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
Tape and reel
SN74AUCH16374DGGR
Tape and reel
SN74AUCH16374DGVR
Tape and reel
SN74AUCH16374GQLR
Tape and reel
SN74AUCH16374ZQLR
TOP-SIDE MARKING
AUCH16374
MJ374
MJ374
MJ374
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DESCRIPTION/ORDERING INFORMATION(CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
2
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Copyright © 2002–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74AUCH16374




 SN74AUCH16374
www.ti.com
GQL or ZQL PACKAGE
(TOP VIEW)
12 34 56
A
B
C
D
E
F
G
H
J
K
SN74AUCH16374
SCES404E – JULY 2002 – REVISED JULY 2012
TERMINAL ASSIGNMENTS(1)
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1CLK
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
VCC
VCC
1D3
1D4
D
1Q6
1Q5
GND
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
VCC
VCC
2D6
2D5
J
2Q7
2Q8
GND
GND
2D8
2D7
K
2OE
NC
NC
NC
NC
2CLK
(1) NC - No internal connection
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OE CLK D
OUTPUT
Q
L
H
H
L
L
L
L H or L X
Q0
H
X
X
Z
Copyright © 2002–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74AUCH16374
Submit Documentation Feedback
3



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