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N-Channel MOSFET. 75309P Datasheet

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N-Channel MOSFET. 75309P Datasheet






75309P MOSFET. Datasheet pdf. Equivalent




75309P MOSFET. Datasheet pdf. Equivalent





Part

75309P

Description

N-Channel MOSFET



Feature


HUF75309P3, HUF75309D3, HUF75309D3S Dat a Sheet December 2001 19A, 55V, 0.070 Ohm, N-Channel UltraFET Power MOSFETs These N-Channel power MOSFETs are manuf actured using the innovative UltraFET® process. This advanced process technol ogy achieves the lowest possible on-res istance per silicon area, resulting in outstanding performance. This device is capable of withsta.
Manufacture

Fairchild Semiconductor

Datasheet
Download 75309P Datasheet


Fairchild Semiconductor 75309P

75309P; nding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It wa s designed for use in applications wher e power efficiency is important, such a s switching regulators, switching conve rters, motor drivers, relay drivers, lo wvoltage bus switches, and power manage ment in portable and battery-operated p roducts. Formerly .


Fairchild Semiconductor 75309P

developmental type TA75309. Ordering In formation PART NUMBER PACKAGE BRAND HUF75309P3 TO-220AB 75309P HUF75309 D3 TO-251AA 75309D HUF75309D3S TO-2 52AA 75309D NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-252AA variant in tap e and reel, e.g., HUF75309D3ST. Packag ing JEDEC STYLE TO-220AB DRAIN (FLANG E) SOURCE DRAIN G.


Fairchild Semiconductor 75309P

ATE Features • 19A, 55V • Simulatio n Models - Temperature Compensated PSPI CE® and SABER™ Models - SPICE and SA BER Thermal Impedance Models Available on the WEB at: www.fairchildsemi.com Peak Current vs Pulse Width Curve • UIS Rating Curve • Related Literatur e - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards Symbol D G S JEDEC TO-251AA DRA.

Part

75309P

Description

N-Channel MOSFET



Feature


HUF75309P3, HUF75309D3, HUF75309D3S Dat a Sheet December 2001 19A, 55V, 0.070 Ohm, N-Channel UltraFET Power MOSFETs These N-Channel power MOSFETs are manuf actured using the innovative UltraFET® process. This advanced process technol ogy achieves the lowest possible on-res istance per silicon area, resulting in outstanding performance. This device is capable of withsta.
Manufacture

Fairchild Semiconductor

Datasheet
Download 75309P Datasheet




 75309P
HUF75309P3, HUF75309D3, HUF75309D3S
Data Sheet
December 2001
19A, 55V, 0.070 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA75309.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF75309P3
TO-220AB
75309P
HUF75309D3
TO-251AA
75309D
HUF75309D3S
TO-252AA
75309D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF75309D3ST.
Packaging
JEDEC STYLE TO-220AB
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
Features
• 19A, 55V
• Simulation Models
- Temperature Compensated PSPICE® and SABER
Models
- SPICE and SABER Thermal Impedance Models
Available on the WEB at: www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-251AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-252AA
GATE
SOURCE
DRAIN
(FLANGE)
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75309P3, HUF75309D3, HUF75309D3S Rev. B




 75309P
HUF75309P3, HUF75309D3, HUF75309D3S
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
55
V
55
V
±20
V
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . .
Derate Above 25oC
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PD
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Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg
19
Figure 4
Figures 6, 14, 15
55
0.37
-55 to 175
300
260
A
W
W/oC
oC
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
VDS = 50V, VGS = 0V
VDS = 45V, VGS = 0V, TC = 150oC
VGS = ±20V
VGS(TH)
rDS(ON)
VGS = VDS, ID = 250µA (Figure 10)
ID = 19A, VGS = 10V (Figure 9)
RθJC
RθJA
(Figure 3)
TO-220
TO-251, TO-252
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
tON
td(ON)
tr
td(OFF)
tf
tOFF
VDD = 30V, ID 19A,
RL = 1.58, VGS = 10V,
RGS = 27
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Reverse Transfer Capacitance
Qg(TOT)
Qg(10)
Qg(TH)
Qgs
Qgd
VGS = 0V to 20V
VGS = 0V to 10V
VGS = 0V to 2V
VDD = 30V,
ID 19A,
RL = 1.58
Ig(REF) = 1.0mA
(Figure13)
MIN TYP MAX UNITS
55
-
-
V
-
-
1
µA
-
-
250
µA
-
-
±100
nA
2
-
4
V
-
0 .060 0.070
-
-
2.7
oC/W
-
-
62
oC/W
-
-
100
oC/W
-
-
70
ns
-
7
-
ns
-
39
-
ns
-
24
-
ns
-
30
-
ns
-
-
80
ns
-
20
24
nC
-
11
13.5
nC
-
0.68 0.85
nC
-
1.8
-
nC
-
5
-
nC
©2001 Fairchild Semiconductor Corporation
HUF75309P3, HUF75309D3, HUF75309D3S Rev. B




 75309P
HUF75309P3, HUF75309D3, HUF75309D3S
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
COSS
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
VSD
trr
QRR
TEST CONDITIONS
ISD = 19A
ISD = 19A, dISD/dt = 100A/µs
ISD = 19A, dISD/dt = 100A/µs
MIN TYP MAX UNITS
-
350
-
pF
-
150
-
pF
-
39
-
pF
MIN
TYP
MAX UNITS
-
-
1.25
V
-
-
50
ns
-
-
70
nC
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125 150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
20
15
10
5
0
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1 0.2
0.1
0.05
0.02
0.01
0.1
0.01
10-5
SINGLE PULSE
10-4
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
HUF75309P3, HUF75309D3, HUF75309D3S Rev. B



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