D Inputs Are TTL-Voltage Compatible D Generates Either Odd or Even Parity for
Nine Data Lines
D Cascadable for n-Bits Parity D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (D) Pack...
