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ACS10MS

Intersil Corporation
Part Number ACS10MS
Manufacturer Intersil Corporation
Description Radiation Hardened Triple Three-Input NAND Gate
Published Mar 23, 2005
Detailed Description ACS10MS April 1995 Radiation Hardened Triple Three-Input NAND Gate Pinouts 14 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DE...
Datasheet PDF File ACS10MS PDF File

ACS10MS
ACS10MS

Overview
ACS10MS April 1995 Radiation Hardened Triple Three-Input NAND Gate Pinouts 14 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C TOP VIEW A1 1 B1 2 A2 3 B2 4 14 VCC 13 C1 12 Y1 11 C3 10 B3 9 A3 8 Y3 Features • 1.
25 Micron Radiation Hardened SOS CMOS • Total Dose 300K RAD (Si) • Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ) • SEU LET Threshold >80 • Dose Rate Upset >1011 MEV-cm2 /mg RAD (Si)/s, 20ns Pulse -55oC +125oC • Latch-Up Free Under Any Conditions • Military Temperature Range: to C2 5 Y2 6 GND 7 • Significant Power Reduction Compared to ALSTTL Logic • DC Operating Voltage Range: 4.
5V to 5.
5V • Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min • Input Current ≤1µA at VOL, VOH 14 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C TOP VIEW A1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC C1 Y1 C3 B3 A3 Y3 Description The Intersil ACS10MS is a radiation hardened triple three-input NAND gate.
A high on all inputs forces the output to a low state.
The ACS10MS utilizes advanced CMOS/SOS technology to achieve high-speed operation.
This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family.
B1 A2 B2 C2 Y2 GND Ordering Information PART NUMBER ACS10DMSR ACS10KMSR ACS10D/Sample ACS10K/Sample ACS10HMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC +25oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 14 Lead SBDIP 14 Lead Ceramic Flatpack 14 Lead SBDIP 14 Lead Ceramic Flatpack Die Truth Table INPUTS An L L L L H H H H Bn L L H H L L H H Cn L H L H L H L H OUTPUT Yn H H H H H H H L Functional Diagram An (1, 3, 9) Bn (2, 4, 10) Yn (6, 8, 12) Cn (5, 11, 13) NOTE: L = Logic Level Low, H = Logic Level High CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 Spec Number 1 518814 Fil...


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