AD9772 Interpolation Filter Datasheet

AD9772 Datasheet, PDF, Equivalent


Part Number

AD9772

Description

14-Bit/ 150 MSPS TxDAC with 2x Interpolation Filter

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download AD9772 Datasheet


AD9772
a
14-Bit, 150 MSPS TxDAC+
with 2؋ Interpolation Filter
AD9772
FEATURES
Single 2.7 V to 3.6 V Supply
14-Bit DAC Resolution and Input Data Width
150 MSPS Input Data Rate
63.3 MHz Reconstruction Passband @ 150 MSPS
75 dBc SFDR @ 25 MHz
2؋ Interpolation Filter with High or Low Pass Response
73 dB Image Rejection with 0.005 dB Passband Ripple
“Zero-Stuffing” Option for Enhanced Direct IF
Performance
Internal 2؋/4؋ Clock Multiplier
205 mW Power Dissipation; 13 mW with Power-Down
Mode
48-Lead LQFP Package
APPLICATIONS
Communication Transmit Channel
WCDMA Base Stations, Multicarrier Base Stations,
Direct IF Synthesis
Instrumentation
PRODUCT DESCRIPTION
The AD9772 is a single supply, oversampling, 14-bit digital-to-
analog converter (DAC) optimized for baseband or IF waveform
reconstruction applications requiring exceptional dynamic range.
Manufactured on an advanced CMOS process, it integrates a
complete, low distortion 14-bit DAC with a 2× digital interpola-
tion filter and clock multiplier. The on-chip PLL clock multi-
plier provides all the necessary clocks for the digital filter and the
14-bit DAC. A flexible differential clock input allows for a single-
ended or differential clock driver for optimum jitter performance.
For baseband applications, the 2× digital interpolation filter
provides a low pass response, hence providing up to a three-fold
reduction in the complexity of the analog reconstruction filter. It
does so by multiplying the input data rate by a factor of two
while simultaneously suppressing the original upper inband
image by more than 73 dB. For direct IF applications, the 2×
digital interpolation filter response can be reconfigured to select
the upper inband image (i.e., high pass response) while sup-
pressing the original baseband image. To increase the signal
level of the higher IF images and their passband flatness in di-
rect IF applications, the AD9772 also features a “zero stuffing”
option in which the data following the 2× interpolation filter is
upsampled by a factor of two by inserting midscale data samples.
The AD9772 can reconstruct full-scale waveforms with band-
widths as high as 63.3 MHz while operating at an input data rate of
150 MSPS. The 14-bit DAC provides differential current out-
puts to support differential or single-ended applications. A
TxDAC+ is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
CLKCOM CLKVDD
MOD0 MOD1 RESET PLLLOCK DIV0 DIV1
CLK+
CLK–
AD9772
CLOCK DISTRIBUTION
AND MODE SELECT
PLL CLOCK
MULTIPLIER
1؋ 1؋/2؋ FILTER
MUX 2؋/4؋
CONTROL CONTROL
PLLCOM
LPF
PLLVDD
DATA
INPUTS
(DB13...DB0)
SLEEP
EDGE-
TRIGGERED
LATCHES
2؋ FIR
INTERPOLATION
FILTER
ZERO
STUFF
MUX
14-BIT DAC
+1.2V REFERENCE
AND CONTROL AMP
IOUTA
IOUTB
REFIO
FSADJ
DCOM DVDD
ACOM AVDD
REFLO
segmented current source architecture is combined with a propri-
etary switching technique to reduce spurious components and
enhance dynamic performance. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The differential current out-
puts may be fed into a transformer or a differential op amp
topology to obtain a single-ended output voltage using an ap-
propriate resistive load.
The on-chip bandgap reference and control amplifier are config-
ured for maximum accuracy and flexibility. The AD9772 can be
driven by the on-chip reference or by a variety of external refer-
ence voltages. The full-scale current of the AD9772 can be
adjusted over a 2 mA to 20 mA range, thus providing additional
gain ranging capabilities.
The AD9772 is available in a 48-lead LQFP package and speci-
fied for operation over the industrial temperature range of –40°C
to +85°C.
PRODUCT HIGHLIGHTS
1. A flexible, low power 2× interpolation filter supporting re-
construction bandwidths of up to 63.3 MHz can be config-
ured for a low or high pass response with 73 dB of image
rejection for traditional baseband or direct IF applications.
2. A “zero-stuffing” option enhances direct IF applications.
3. A low glitch, fast settling 14-bit DAC provides exceptional
dynamic range for both baseband and direct IF waveform
reconstruction applications.
4. The AD9772 digital interface, consisting of edge-triggered
latches and a flexible differential or single-ended clock input,
can support input data rates up to 150 MSPS.
5. On-chip PLL clock multiplier generates all of the internal high
speed clocks required by the interpolation filter and DAC.
6. The current output(s) of the AD9772 can easily be configured
for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

AD9772
AD9772–SPECIFICATIONS
DC SPECIFICATIONS (TMIN to TMAX, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = 0 V, DVDD = +3 V, IOUTFS = 20 mA, unless otherwise
noted)
Parameter
Min Typ Max
Units
RESOLUTION
DC ACCURACY1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
Monotonicity (12-Bit)
14
± 3.5
± 2.0
Guaranteed Over Specified Temperature Range
Bits
LSB
LSB
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
–0.025
–2
–5
–1.0
± 0.5
± 1.5
20
200
3
+0.025
+2
+5
+1.25
% of FSR
% of FSR
% of FSR
mA
V
k
pF
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (REFLO = 3 V)
Small Signal Bandwidth
1.14 1.20 1.26
1
0.1 1.25
10
0.5
V
µA
V
M
MHz
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
AVDD
Voltage Range
Analog Supply Current (IAVDD)
Analog Supply Current in SLEEP Mode (IAVDD)
PLLVDD4
Voltage Range
PLL Clock Multiplier Supply Current (IPLLVDD)
CLKVDD
Voltage Range
Clock Supply Current (ICLKVDD)
DVDD5
Voltage Range
Digital Supply Current (IDVDD)
Nominal Power Dissipation5
Power Supply Rejection Ratio (PSRR)6 – AVDD
Power Supply Rejection Ratio (PSRR)6 – DVDD
OPERATING RANGE
NOTES
1Measured at IOUTA driving a virtual ground.
2Nominal full-scale current, IOUTFS, is 32× the IREF current.
3Use an external amplifier to drive any external load.
4Measured at fDATA = 100 MSPS and fOUT = 1 MHz, PLLVDD = 3.0 V.
5Measured at fDATA = 50 MSPS and fOUT = 1 MHz.
6Measured over a 2.7 V to 3.6 V range.
Specifications subject to change without notice.
2.7
2.7
2.7
2.7
–0.6
–0.025
–40
0
± 50
± 100
± 50
3.0
34
4.3
3.0
4.5
3.0
5.5
3.0
29
205
3.6
37
6
3.6
6
3.6
7
3.6
33
231
+0.6
+0.025
+85
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
V
mA
mA
V
mA
V
mA
V
mA
mW
% of FSR/V
% of FSR/V
°C
–2– REV. 0


Features a FEATURES Single 2.7 V to 3.6 V Supply 14-Bit DAC Resolution and Input Data Wi dth 150 MSPS Input Data Rate 63.3 MHz R econstruction Passband @ 150 MSPS 75 dB c SFDR @ 25 MHz 2؋ Interpolation Filte r with High or Low Pass Response 73 dB Image Rejection with 0.005 dB Passband Ripple “Zero-Stuffing” Option for E nhanced Direct IF Performance Internal 2 ؋ /4؋ Clock Multiplier 205 mW Power Dissipation; 13 mW with Power-Down Mod e 48-Lead LQFP Package APPLICATIONS Com munication Transmit Channel WCDMA Base Stations, Multicarrier Base Stations, D irect IF Synthesis Instrumentation PROD UCT DESCRIPTION 14-Bit, 150 MSPS TxDAC +™ with 2؋ Interpolation Filter AD97 72 FUNCTIONAL BLOCK DIAGRAM CLKCOM CLKV DD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1 A D9772 CLK+ CLK– 1؋ 1؋/2؋ CLOCK DIS TRIBUTION AND MODE SELECT FILTER CONTRO L MUX CONTROL 2؋/4؋ PLL CLOCK MULTIPL IER PLLCOM LPF PLLVDD DATA INPUTS (DB 13...DB0) EDGETRIGGERED LATCHES 2؋ F IR INTERPOLATION FILTER ZERO STUFF MUX IOUTA 14-BIT DAC IOUTB REFIO FSADJ SLEE.
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