D/A Converter. AD9773 Datasheet


AD9773 Converter. Datasheet pdf. Equivalent


Part Number

AD9773

Description

Dual TxDAC D/A Converter

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download AD9773 Datasheet


AD9773
12-Bit, 160 MSPS, 2×/4×/8× Interpolating
Dual TxDAC D/A Converter
AD9773
FEATURES
12-bit resolution, 160 MSPS/400 MSPS
input/output data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
fS/2, fS/4, fS/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI port
Excellent ac performance
SFDR −69 dBc @ 2 MHz to 35 MHz
WCDMA ACPR −69 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or
TTL/CMOS/LVPECL compatible
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
Power dissipation: typical 1.2 W @ 3.3 V
On-chip 1.2 V reference
80-lead thin quad flat package, exposed pad (TQFP_EP)
APPLICATIONS
Communications
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
FUNCTIONAL BLOCK DIAGRAM
AD9773
12
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
12
DATA
ASSEMBLER
HALF-
BAND
FILTER1*
I 16
LATCH
16
HALF- HALF-
BAND
BAND
FILTER2* FILTER3*
16 16
Q 16
LATCH
16
16 16
COS
SIN
fDAC/2, 4, 8
SIN
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
WRITE
SELECT
MUX
CONTROL
CLOCK OUT
/2
SPI INTERFACE AND
CONTROL REGISTERS
/2
/2
* HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR ZERO STUFFING ONLY
FILTER
BYPASS
MUX
/2
COS
(fDAC)
PRESCALER
PHASE DETECTOR
AND VCO
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
Figure 1.
IDAC
GAIN
DAC
OFFSET
DAC
I/Q DAC
GAIN/OFFSET
REGISTERS
IDAC
IOUT
DIFFERENTIAL
CLK
Rev. D
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.

AD9773
AD9773* Product Page Quick Links
Last Content Update: 11/01/2016
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Documentation
Application Notes
• AN-137: A Digitally Programmable Gain and Attenuation
Amplifier Design
• AN-237: Choosing DACs for Direct Digital Synthesis
• AN-302: Exploit Digital Advantages in an SSB Receiver
• AN-320A: CMOS Multiplying DACs and Op Amps
Combine to Build Programmable Gain Amplifier, Part 1
• AN-595: Understanding Pin Compatibility in the TxDAC®
Line of High Speed D/A Converters
• AN-642: Coupling a Single-Ended Clock Source to the
Differential Clock Input of Third-Generation TxDAC® and
TxDAC+® Products
• AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
Data Sheet
• AD9773: 12-Bit, 160 MSPS 2x/4x/8x Interpolating Dual
TxDAC® D/A Converter Data Sheet
Tools and Simulations
• AD9773 IBIS Models
Reference Materials
Informational
• Advantiv™ Advanced TV Solutions
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Design Resources
• AD9773 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
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Features 12-Bit, 160 MSPS, 2×/4×/8× Interpolat ing Dual TxDAC D/A Converter AD9773 FE ATURES 12-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2×/4×/8× interpolating filter Progra mmable channel gain and offset adjustme nt fS/2, fS/4, fS/8 digital quadrature modulation capability Direct IF transmi ssion mode for 70 MHz + IFs Enables ima ge rejection architecture Fully compati ble SPI port Excellent ac performance S FDR −69 dBc @ 2 MHz to 35 MHz WCDMA A CPR −69 dB @ IF = 19.2 MHz Internal P LL clock multiplier Selectable internal clock divider Versatile clock input Di fferential/single-ended sine wave or TT L/CMOS/LVPECL compatible Versatile inp ut data interface Twos complement/strai ght binary data coding Dual-port or sin gle-port interleaved input data Single 3.3 V supply operation Power dissipatio n: typical 1.2 W @ 3.3 V On-chip 1.2 V reference 80-lead thin quad flat packag e, exposed pad (TQFP_EP) APPLICATIONS C ommunications Analog quadrature modulation architecture 3G, multicarrier .
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