Row Driver. HV6008 Datasheet
32-Channel ±40V Liquid Crystal Display Row Driver
44-J Lead Quad
Plastic Chip Carrier
44 -J Lead Quad
Ceramic Chip Carrier
44-Lead Quad Plastic
❏ Symmetrical ± 40V output swing
❏ Active return to GND
❏ 15mA peak source/sink/GND current per channel
❏ +5V control logic
❏ Special shift register with clear
❏ Phase shift control
❏ Output enable
❏ Data out enable
❏ 1MHz shift register
❏ Surface mount package available
Not recommended for new designs.
The HV60 is a 32-channel liquid crystal display driver with 3-state
DMOS outputs. Each output can be set to +40V, -40V, or GND.
A symmetric waveform can be applied to a capacitive load using
the phase shift feature of the HV60.
The HV60 consists of a 32-bit shift register with Clear, Enable, and
Phase Shift logic, and 32 high voltage output buffers. With the
Enable pin held low, all outputs are placed in the return to zero
(GND) state. When Enable is high, each output reflects the data
in its shift register bit. All outputs with a logic “0” in their shift
register will be in the return to zero state. Outputs with a logic “1”
in their shift register will reflect the state of the phase shift pin.
These outputs will be switched to VPP when phase shift is high and
VNN when phase shift is logic “0”.
Additional functions provided are Shift Register Clear and Data
Out. All bits of the shift register are changed to logic “0” when Clear
is pulled low. With Clear at a logic “1”, normal shift register
operation proceeds. The data output reflects the status of the
32nd shift register stage.
Absolute Maximum Ratings
Supply voltage, VDD11
Supply voltage, VDD21
Supply voltage, VPP1,2
Supply voltage, VNN1,2
Logic input levels1
VDD1 - 0.3V to VDD2 + 0.3V
Continuous total power dissipation3
Operating temperature range
-40°C to +85°C
Storage temperature range
-65°C to +150°C
1. All voltages are referenced to GND.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to 85°C at 16.7mW/°C.
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workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
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Electrical Characteristics (over recommended operating conditions unless noted)
VDD supply current
Logic input high
Logic input low
Logic output high
Logic output low
VI = 4V, VDD1 = -6V
VI = 4V, VDD2 = +6V
V VDD1 = -4.5V,
V VDD2 = +4.5V
V VDD1 = -4.5V
VDD2 = +4.5V
V IOH = -15µA
IOL = 250µA
IIH High-level logic input current
+3 µA VI = VDD, VDD1,2 = max
IIL Low-level logic input current
-50 µA VI = 0V, VDD1,2 = max
IPP High voltage supply current
+1 mA Static, no load
INN High voltage supply current
-1 mA Static, no load
VOH Output voltage high
VCL Output voltage clamp
+39 V VPP, VNN = ±40
-20 +20 mV No load
VOL Output voltage low
ZOH Output switch impedence high
ZCL Output switch impedance clamp
ZOL Output switch impedance low
Ω VPP, VNN = ±40
IO = ±15mA
IO DC output current Output H or L
5 mA 1 output only
Data out H or L
tWH Width of high data pulse
tWL Width of low data pulse
tSU Data set-up time before clock falls
tH Data hold time after clock falls
Phase shift duty cycle
Min Typ Max Units Conditions
Recommended Operating Conditions
Logic supply voltage
Logic supply voltage
VPP High voltage supply
VNN High voltage supply
VIH High-level input voltage
VIL Low-level input voltage
Peak output current (any state)
TA Operating free-air temperature
fDIN Input data rate
fPS Phase shift rate
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
Power-down sequence should be the reverse of the above.
Min Typ Max
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply VPP and VNN.