Loop Buffer. HS-1412RH Datasheet

HS-1412RH Buffer. Datasheet pdf. Equivalent

Part HS-1412RH
Description Radiation Hardened/ Quad/ High Speed/ Low Power/ Video Closed Loop Buffer
Feature HS-1412RH Data Sheet August 1999 File Number 4230.1 Radiation Hardened, Quad, High Speed, Low Power.
Manufacture Intersil Corporation
Datasheet
Download HS-1412RH Datasheet



HS-1412RH
Data Sheet
HS-1412RH
August 1999 File Number 4230.1
Radiation Hardened, Quad, High Speed,
Low Power, Video Closed Loop Buffer
The HS-1412RH is a radiation hardened quad closed loop
buffer featuring user programmable gain and high speed
performance. Manufactured on Intersil’s proprietary
complementary bipolar UHF-1 (DI bonded wafer) process,
this device offers wide -3dB bandwidth of 340MHz, very fast
slew rate, excellent gain flatness and high output current.
These devices are QML approved and are processed and
screened in full compliance with MIL-PRF-38535.
A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components. Gain selection is accomplished via
connections to the inputs, as described in the “Application
Information” section. The result is a more flexible product,
fewer part types in inventory, and more efficient use of board
space.
Compatibility with existing op amp pinouts provides flexibility
to upgrade low gain amplifiers, while decreasing component
count. Unlike most buffers, the standard pinout provides an
upgrade path should a higher closed loop gain be needed at
a future date.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96834. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
5962F9683401VCA
HS1-1412RH-Q
5962F9683401VCC
HS1B-1412RH-Q
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
Features
• Electrically Screened to SMD # 5962-96834
• QML Qualified per MIL-PRF-38535 Requirements
• MIL-PRF-38535 Class V Compliant
• User Programmable For Closed-Loop Gains of +1, -1 or
+2 Without Use of External Resistors
• Standard Operational Amplifier Pinout
• Low Supply Current . . . . . . . . . . . . 5.9mA/Op Amp (Typ)
• Excellent Gain Accuracy . . . . . . . . . . . . . . . 0.99V/V (Typ)
• Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . .340MHz (Typ)
• Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . .1155V/µs (Typ)
• High Input Impedance . . . . . . . . . . . . . . . . . . . 1M(Typ)
• Excellent Gain Flatness (to 50MHz). . . . . . ±0.02dB (Typ)
• Fast Overdrive Recovery . . . . . . . . . . . . . . . . <10ns (Typ)
• Total Gamma Dose. . . . . . . . . . . . . . . . . . . . 300kRAD(Si)
• Latch Up . . . . . . . . . . . . . . . . . . . . . None (DI Technology)
Applications
• Flash A/D Driver
• Video Switching and Routing
• Pulse and Video Amplifiers
• Wideband Amplifiers
• RF/IF Signal Processing
• Imaging Systems
Pinout
HS-1412RH (CERDIP) GDIP1-T14
OR
HS-1412RH (SBDIP) CDIP2-T14
TOP VIEW
OUT1 1
-IN1 2
+IN1 3
V+ 4
+IN2 5
-IN2 6
OUT2 7
14 OUT4
13 -IN4
12 +IN4
11 V-
10 +IN3
9 -IN3
8 OUT3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999



HS-1412RH
HS-1412RH
Application Information
HS-1412RH Advantages
The HS-1412RH features a novel design which allows the
user to select from three closed loop gains, without any
external components. The result is a more flexible product,
fewer part types in inventory, and more efficient use of board
space. Implementing a quad, gain of 2, cable driver with this
IC eliminates the eight gain setting resistors, which frees up
board space for termination resistors.
Like most newer high performance amplifiers, the HS-1412RH
is a current feedback amplifier (CFA). CFAs offer high
bandwidth and slew rate at low supply currents, but can be
difficult to use because of their sensitivity to feedback
capacitance and parasitics on the inverting input (summing
node). The HS-1412RH eliminates these concerns by bringing
the gain setting resistors on-chip. This yields the optimum
placement and value of the feedback resistor, while minimizing
feedback and summing node parasitics. Because there is no
access to the summing node, the PCB parasitics do not impact
performance at gains of +2 or -1 (see “Unity Gain
Considerations” for discussion of parasitic impact on unity gain
performance).
The HS-1412RH’s closed loop gain implementation provides
better gain accuracy, lower offset and output impedance,
and better distortion compared with open loop buffers.
Closed Loop Gain Selection
This “buffer” operates in closed loop gains of -1, +1, or +2,
with gain selection accomplished via connections to the
±inputs. Applying the input signal to +IN and floating -IN
selects a gain of +1 (see next section for layout caveats),
while grounding -IN selects a gain of +2. A gain of -1 is
obtained by applying the input signal to -IN with +IN
grounded through a 50resistor.
The table below summarizes these connections:
GAIN
(ACL)
-1
+1
+2
CONNECTIONS
+INPUT
-INPUT
50to GND
Input
Input
NC (Floating)
Input
GND
Unity Gain Considerations
Unity gain selection is accomplished by floating the -Input of
the HS-1412RH. Anything that tends to short the -Input to
GND, such as stray capacitance at high frequencies, will
cause the amplifier gain to increase toward a gain of +2. The
result is excessive high frequency peaking, and possible
instability. Even the minimal amount of capacitance
associated with attaching the -Input lead to the PCB results
in approximately 6dB of gain peaking. At a minimum this
requires due care to ensure the minimum capacitance at the
-Input connection.
Table 1 lists five alternate methods for configuring the
HS-1412RH as a unity gain buffer, and the corresponding
performance. The implementations vary in complexity and
involve performance trade-offs. The easiest approach to
implement is simply shorting the two input pins together,
and applying the input signal to this common node. The
amplifier bandwidth decreases from 550MHz to 370MHz,
but excellent gain flatness is the benefit. A drawback to this
approach is that the amplifier input noise voltage and input
offset voltage terms see a gain of +2, resulting in higher
noise and output offset voltages. Alternately, a 100pF
capacitor between the inputs shorts them only at high
frequencies, which prevents the increased output offset
voltage but delivers less gain flatness.
Another straightforward approach is to add a 620resistor
in series with the amplifier’s positive input. This resistor and
the HS-1412RH input capacitance form a low pass filter
which rolls off the signal bandwidth before gain peaking
occurs. This configuration was employed to obtain the data
sheet AC and transient parameters for a gain of +1.
Pulse Overshoot
The HS-1412RH utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent
supply current. In this approach, a composite device replaces
the traditional PNP pulldown transistor. The composite device
switches modes after crossing 0V, resulting in added
distortion for signals swinging below ground, and an
increased overshoot on the negative portion of the output
waveform (see Figure 5, Figure 7, and Figure 9). This
overshoot isn’t present for small bipolar signals (see Figure 4,
Figure 6, and Figure 8) or large positive signals. Figure 28
through Figure 31 illustrate the amplifier’s overshoot
dependency on input transition time, and signal polarity.
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS
APPROACH
PEAKING (dB)
BW (MHz)
SR (V/µs)
±0.1dB GAIN FLATNESS (MHz)
Remove -IN Pin
5.0 550 1300
18
+RS = 620
+RS = 620and Remove -IN Pin
Short +IN to -IN (e.g., Pins 2 and 3)
1.0 230 1000
0.7 225 1000
0.1 370 500
25
28
170
100pF Capacitor Between +IN and -IN
0.3 380 550
130
2







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)