CMOS Microprocessor. HS1-80C86RH Datasheet

HS1-80C86RH Microprocessor. Datasheet pdf. Equivalent

Part HS1-80C86RH
Description Radiation Hardened 16-Bit CMOS Microprocessor
Feature HS-80C86RH September 1995 Radiation Hardened 16-Bit CMOS Microprocessor Description The Intersil HS.
Manufacture Intersil Corporation
Datasheet
Download HS1-80C86RH Datasheet



HS1-80C86RH
HS-80C86RH
September 1995
Radiation Hardened
16-Bit CMOS Microprocessor
Features
Description
• Radiation Hardened
- Latch Up Free EPl-CMOS
- Total Dose >100K RAD (Si)
- Transient Upset >108 RAD (Si)/s
• Low Power Operation
- ICCSB = 500µA (Max)
- ICCOP = 12mA/MHz (Max)
The Intersil HS-80C86RH high performance radiation
hardened 16-bit CMOS CPU is manufactured using a
hardened field, self aligned silicon gate CMOS process. Two
modes of operation, MINimum for small systems and
MAXimum for larger applications such as multiprocessing,
allow user configuration to achieve the highest performance
level. Industry standard operation allows use of existing
NMOS 8086 hardware and software designs.
• Pin Compatible with NMOS 8086 and Intersil 80C86
• Completely Static Design DC to 5MHz
• 1MB Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word, and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary or Decimal
- Multiply and Divide
• Bus-hold Circuitry Eliminates Pull-up Resistors for
CMOS Designs
• Hardened Field, Self-Aligned, Junction-Isolated CMOS
Process
• Single 5V Power Supply
• Military Temperature Range -35oC to +125oC
• Minimum LET for Single Event Upset -6MEV/mg/cm2
(Typ)
Ordering Information
PART NUMBER
HS1-80C86RH-8
HS1-80C86RH-Q
HS9-80C86RH-8
HS9-80C86RH-Q
HS9-80C86RH-SAMPLE
HS1-80C86RH-SAMPLE
HS9-80C86RH-PROTO
HS1-80C86RH-PROTO
TEMPERATURE RANGE
-35oC to +125oC
-35oC to +125oC
-35oC to +125oC
-35oC to +125oC
25oC
25oC
-35oC to +125oC
-35oC to +125oC
SCREENING LEVEL
Intersil Class B Equivalent
Intersil Class S Equivalent
Intersil Class B Equivalent
Intersil Class S Equivalent
Sample
Sample
Prototype
Prototype
PACKAGE
40 Lead Braze Seal DIP
40 Lead Braze Seal DIP
42 Lead Braze Seal Flatpack
42 Lead Braze Seal Flatpack
42 Lead Braze Seal Flatpack
40 Lead Braze Seal DIP
42 Lead Braze Seal Flatpack
40 Lead Braze Seal DIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
856
Spec Number 518055
File Number 3035.1



HS1-80C86RH
Pinouts
HS-80C86RH
HS-80C86RH 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835, CDIP2-T40
TOP VIEW
GND 1
AD14 2
AD13 3
AD12 4
AD11 5
AD10 6
AD9 7
AD8 8
AD7 9
AD6 10
AD5 11
AD4 12
AD3 13
AD2 14
AD1 15
AD0 16
NMI 17
INTR 18
CLK 19
GND 20
MAX
40 VDD
MIN
39 AD15
38 AD16/S3
37 A17/S4
36 A18/S5
35 A19/S6
34 BHE/S7
33 MN/MX
32 RD
31 RQ/GT0 (HOLD)
30 RQ/GT1 (HLDA)
29 LOCK (WR)
28 S2
(M/IO)
27 S1
(DT/R)
26 S0
25 QS0
24 QS1
23 TEST
22 READY
21 RESET
(DEN)
(ALE)
(INTA)
HS-80C86RH 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK)
INTERSIL OUTLINE K42.A
TOP VIEW
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NC
NMI
INTR
CLK
GND
1 42
2 41
3 40
4 39
5 38
6 37
7 36
8 35
9 34
10 33
11 32
12 31
13 30
14 29
15 28
16 27
17 26
18 25
19 24
20 23
21 22
MAX
VDD
MIN
AD15
NC
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
RQ/GT0 (HOLD)
RQ/GT1 (HLDA)
LOCK (WR)
S2 (M/IO)
S1 (DT/R)
S0 (DEN)
QS0
(ALE)
QS1
(INTA)
TEST
READY
RESET
Spec Number 518055
857







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