DMA Controller. HS1-82C37ARH-Q Datasheet

HS1-82C37ARH-Q Controller. Datasheet pdf. Equivalent

Part HS1-82C37ARH-Q
Description Radiation Hardened CMOS High Performance Programmable DMA Controller
Feature S E M I C O N D U C T O R HS-82C37ARH Radiation Hardened CMOS High Performance Programmable DMA Con.
Manufacture Harris Corporation
Datasheet
Download HS1-82C37ARH-Q Datasheet




HS1-82C37ARH-Q
SEMICONDUCTOR
HS-82C37ARH
August 1995
Radiation Hardened CMOS High
Performance Programmable DMA Controller
Features
Description
• Radiation Hardened
- Total Dose >105 RAD (Si)
- Transient Upset > 108 RAD (Si)/s
- Latch Up Free EPI-CMOS
• Low Power Consumption
- IDDSB = 50µA Maximum
- IDDOP = 4.0mA/MHz Maximum
• Pin Compatible with NMOS 8237A and the Harris
82C37A
The Harris HS-82C37ARH is an enhanced, radiation
hardened CMOS version of the industry standard 8237A
Direct Memory Access (DMA) controller, fabricated using the
Harris hardened field, self-aligned silicon gate CMOS
process. The HS-82C37ARH offers increased functionality,
improved performance, and dramatically reduced power
consumption for the radiation environment. The high speed,
radiation hardness, and industry standard configuration of
the HS-82C37ARH make it compatible with radiation
hardened microprocessors such as the HS-80C85RH and
the HS-80C86RH.
• High Speed Data Transfers Up To 2.5 MBPS With 5MHz
Clock
• Four Independent Maskable Channels With Autoinitializa-
tion Capability
• Expandable to Any Number of Channels
• Memory-to-Memory Transfer Capability
• CMOS Compatible
• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process
• Single 5V Supply
• Military Temperature Range -55oC to +125oC
The HS-82C37ARH can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization
feature. DMA requests may be generated by either
hardware or software, and each channel is independently
programmable with a variety of features for flexible
operation.
Static CMOS circuit design insures low operating power and
allows gated clock operation for an even further reduction of
power. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
The Harris hardened field CMOS process results in
performance equal to or greater than existing radiation resis-
tant products at a fraction of the power.
Ordering Information
PART NUMBER
HS1-82C37ARH-Q
HS1-82C37ARH-8
HS1-82C37ARH-Sample
HS9-82C37ARH-Q
HS9-82C37ARH-8
HS9-82C37ARH/Sample
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
-55oC to +125oC
-55oC to +125oC
+25oC
PACKAGE
40 Lead SBDIP
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1995
1
Spec Number 518058
File Number 3042.1



HS1-82C37ARH-Q
HS-82C37ARH
Pinouts
40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835 CDIP2-T40
TOP VIEW
IOR 1
IOW 2
MEMR 3
MEMW 4
NC 5
READY 6
HLDA 7
ADSTB 8
AEN 9
HRQ 10
CS 11
CLK 12
RESET 13
DACK2 14
DACK3 15
DREQ3 16
DREQ2 17
DREQ1 18
DREQ0 19
(GND) 20
VSS
40 A7
39 A6
38 A5
37 A4
36 EOP
35 A3
34 A2
33 A1
32 A0
31 VDD
30 DB0
29 DB1
28 DB2
27 DB3
26 DB4
25 DACK0
24 DACK1
23 DB5
22 DB6
21 DB7
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) HARRIS OUTLINE K42.A
TOP VIEW
IOR
IOW
MEMR
MEMW
NC
READY
HLDA
ADSTB
AEN
HRQ
CS
CLK
RESET
DACK2
DACK3
NC
DREQ3
DREQ2
DREQ1
DREQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 A7
41 A6
40 A5
39 A4
38 EOP
37 A3
36 A2
35 A1
34 A0
33 VDD
32 DB0
31 DB1
30 DB2
29 DB3
28 DB4
27 NC
26 DACK0
25 DACK1
24 DB5
23 DB6
22 DB7
Functional Diagram
EOP
RESET
CS
READY
CLOCK
AEN
ADSTB
MEMR
MEMW
IOR
IOW
TIMING
AND
CONTROL
DREQ0-
DREQ3
HLDA
HDQ
DACK0-
DACK3
4
4
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
DECREMENTOR
TEMP WORD
COUNT REG (16)
16 BIT BUS
READ BUFFER
BASE
ADDRESS
(16)
BASE
WORD
COUNT
(16)
INC DECREMENTOR
TEMP ADDRESS
REG (16)
16 BIT BUS
BASE
ADDRESS
(16)
BASE
WORD
COUNT
(16)
I/O BUFFER
A0-A3
OUTPUT
BUFFER
A4-A7
COMMAND
CONTROL
COMMAND (8)
MASK (4)
REQUEST (4)
WRITE
BUFFER
READ
BUFFER
INTERNAL DATA BUS
D0-D1
I/O BUFFER
DB0-DB7
MODE
(4 x 6)
STATUS (8)
TEMPORARY
(8)
Spec Number 518058
2







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