Digital Filter. HSP43881 Datasheet

HSP43881 Filter. Datasheet pdf. Equivalent

Part HSP43881
Description Digital Filter
Feature HSP43881 Data Sheet May 1999 File Number 2758.4 Digital Filter The HSP43881 is a video speed Digita.
Manufacture Intersil Corporation
Datasheet
Download HSP43881 Datasheet

HSP43881 Data Sheet May 1999 File Number 2758.4 Digital Fil HSP43881 Datasheet
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HSP43881
Data Sheet
HSP43881
May 1999 File Number 2758.4
Digital Filter
The HSP43881 is a video speed Digital Filter (DF) designed
to efficiently implement vector operations such as FIR digital
filters. It is comprised of eight filter cells cascaded internally
and a shift and add output stage, all in a single integrated
circuit. Each filter cell contains a 8 x 8-bit multiplier, three
decimation registers and a 26-bit accumulator. The output
stage contains an additional 26-bit accumulator which can
add the contents of any filter cell accumulator to the output
stage accumulator shifted right by 8 bits. The HSP43881 has
a maximum sample rate of 30MHz. The effective multiply
accumulate (mac) rate is 240MHz.
The HSP43881 DF can be configured to process expanded
coefficient and word sizes. Multiple DFs can be cascaded for
larger filter lengths without degrading the sample rate or a
single DF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or two’s complement
arithmetic, independently selectable for coefficients and
signal data.
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of 1/2, 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and N x N spatial
correlations/convolutions for image processing applications.
Features
• Eight Filter Cells
• 0MHz to 30MHz Sample Rate
• 8-Bit Coefficients and Signal Data
• 26-Bit Accumulator Per Stage
• Filter Lengths Over 1000 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
• Sample Rate Converters
Ordering Information
PART
NUMBER
HSP43881JC-20
HSP43881JC-25
TEMP. RANGE
(oC)
PACKAGE
0 to 70
84 Ld PLCC
0 to 70
84 Ld PLCC
PKG. NO.
N84.1.15
N84.1.15
HSP43881JC-30
HSP43881GC-20
HSP43881GC-25
0 to 70
0 to 70
0 to 70
84 Ld PLCC
85 Ld PGA
85 Ld PGA
N84.1.15
G85.A
G85.A
HSP43881GC-30
0 to 70
85 Ld PGA G85.A
Block Diagram
VCC VSS
DIN0 - DIN7 TCS
DIENB
CIENB
DCMO - 1
ERASE
5
8
TCCI
CIN0 - 7 8
DF
FILTER 8
CELL 0
RESET 5
CLK
ADR0 - 2
5
3
26
8
8
DF
FILTER 8
CELL 1
26
8
DF
FILTER 8
CELL 2
26
8
DF
FILTER 8
CELL 3
26
MUX
RESET
CLK
SHADD
SENBL
SENBH
ADR0, ADR1, ADR2
2
2
26
OUTPUT
STAGE
26
SUM0 - 25
8
DF
FILTER 8
CELL 4
26
8
DF
FILTER 8
CELL 5
26
8
DF
FILTER 8
CELL 6
26
8
DF
FILTER 8
CELL 7
26
TCCO
COUT0 - 7
COENB
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999



HSP43881
Pinouts
HSP43881
85 PIN GRID ARRAY (PGA)
TOP VIEW, PINS DOWN
1 2 3 4 5 6 7 8 9 10 11
A VSS COENB VCC RESET DIN7 DIN6 DIN3 DIN0 TCCI VCC VSS
B VCC COUT7 TCCO ERASE TCS DIN1 DIN2 CIENB CIN7 CIN6 CIN4
C
COUT5 COUT6
ALIGN
PIN
DIENB DIN5 DIN4
CIN5 CIN3
D COUT3 COUT4
CIN2 VCC
E COUT1 VSS COUT2
CIN1 CIN0 SENBL
F VSS COUT0 SHADD
SUM0 VCC VSS
G ADR2 DCM0 CLK
SUM1 SUM3 SUM2
H ADR1 ADR0
SUM5 SUM4
J VCC SUM25
SUM20 SUM17 SUM16
SUM7 VSS
K SENBH SUM24 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6
L DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9
HSP43881
TOP VIEW, PINS UP
1 2 3 4 5 6 7 8 9 10 11
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9
K
SENBH SUM24 VSS
VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6
J
VCC SUM25
H
ADR1 ADR0
G
ADR2 DCM0 CLK
F
VSS COUT0 SHADD
E
COUT1 VSS COUT2
D
COUT3 COUT4
SUM20 SUM17 SUM16
SUM7 VSS
SUM5 SUM4
SUM1 SUM3 SUM2
SUM0 VCC
VSS
CIN1 CIN0 SENBL
CIN2 VCC
C
COUT5 COUT6 ALIGN
PIN
B
DIENB DIN5 DIN4
CIN5 CIN3
VCC COUT7 COUT8 ERASE DIN8 DIN1 DIN2 CIENB CIN7 CIN6 CIN4
A
VSS COENB VCC RESET DIN7 DIN6 DIN3 DIN0 CIN8 VCC VSS
2





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