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CMOS RAM. HM-6516 Datasheet

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CMOS RAM. HM-6516 Datasheet






HM-6516 RAM. Datasheet pdf. Equivalent




HM-6516 RAM. Datasheet pdf. Equivalent





Part

HM-6516

Description

2K x 8 CMOS RAM



Feature


HM-6516 March 1997 2K x 8 CMOS RAM Desc ription The HM-6516 is a CMOS 2048 x 8 Static Random Access Memory. Extremely low power operation is achieved by the use of complementary MOS design techniq ues. This low power is further enhanced by the use of synchronous circuit tech niques that keep the active (operating) power low, which also gives fast acces s times. The pinou.
Manufacture

Intersil Corporation

Datasheet
Download HM-6516 Datasheet


Intersil Corporation HM-6516

HM-6516; t of the HM-6516 is the popular 24 pin, 8-bit wide JEDEC standard, which allows easy memory board layouts, flexible e nough to accommodate a variety of PROMs , RAMS, EPROMs, and ROMs. The HM-6516 i s ideally suited for use in microproces sor based systems. The byte wide organi zation simplifies the memory array des ign, and keeps operating power down to a minimum, because onl.


Intersil Corporation HM-6516

y one device is enabled at a time. The a ddress latches allow very simple interf acing to recent generation microprocess ors which employ a multiplexed address/ data bus. The convenient output enable control also simplifies multiplexed bu s interfacing by allowing the data outp uts to be controlled independent of the chip enable. Features • Low Power S tandby . . . . . . . ..


Intersil Corporation HM-6516

. . . . . . . . . . . 275µW Max • Lo w Power Operation . . . . . . . . . . . . . 55mW/MHz Max • Fast Access Time. . . . . . . . . . . . . . . . . . 120/ 200ns Max • Industry Standard Pinout • Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC • TTL Compatible • Static Memory C ells • High Output Drive • On-Chip Address Latches • Easy Microprocess.

Part

HM-6516

Description

2K x 8 CMOS RAM



Feature


HM-6516 March 1997 2K x 8 CMOS RAM Desc ription The HM-6516 is a CMOS 2048 x 8 Static Random Access Memory. Extremely low power operation is achieved by the use of complementary MOS design techniq ues. This low power is further enhanced by the use of synchronous circuit tech niques that keep the active (operating) power low, which also gives fast acces s times. The pinou.
Manufacture

Intersil Corporation

Datasheet
Download HM-6516 Datasheet




 HM-6516
HM-6516
March 1997
2K x 8 CMOS RAM
Features
Description
• Low Power Standby . . . . . . . . . . . . . . . . . . . 275µW Max
• Low Power Operation . . . . . . . . . . . . . 55mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• Industry Standard Pinout
• Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC
• TTL Compatible
• Static Memory Cells
• High Output Drive
• On-Chip Address Latches
• Easy Microprocessor Interfacing
The HM-6516 is a CMOS 2048 x 8 Static Random Access
Memory. Extremely low power operation is achieved by the
use of complementary MOS design techniques. This low
power is further enhanced by the use of synchronous circuit
techniques that keep the active (operating) power low, which
also gives fast access times. The pinout of the HM-6516 is
the popular 24 pin, 8-bit wide JEDEC standard, which allows
easy memory board layouts, flexible enough to accommo-
date a variety of PROMs, RAMS, EPROMs, and ROMs.
The HM-6516 is ideally suited for use in microprocessor
based systems. The byte wide organization simplifies the
memory array design, and keeps operating power down to a
minimum, because only one device is enabled at a time. The
address latches allow very simple interfacing to recent gen-
eration microprocessors which employ a multiplexed
address/data bus. The convenient output enable control also
simplifies multiplexed bus interfacing by allowing the data
outputs to be controlled independent of the chip enable.
Ordering Information
120ns
HM1-6516B-9
-
8403607JA
-
8403607ZA
Pinouts
HM-6516
(CERDIP)
TOP VIEW
200ns
HM1-6516-9
29102BJA
8403601JA
HM4-6516-9
8403601ZA
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
PACKAGE
CERDIP
JAN#
SMD#
CLCC
SMD#
HM-6516
(CLCC)
TOP VIEW
PKG. NO.
F24.6
F24.6
F24.6
J32.A
J32.A
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
DQ0 9
DQ1 10
DQ2 11
GND 12
24 VCC
23 A8
22 A9
21 W
20 G
19 A10
18 E
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 NC
A3 8
26 W
A2 9
25 G
A1 10
24 A10
A0 11
23 E
NC 12
22 DQ7
DQ0 13
21 DQ6
14 15 16 17 18 19 20
PIN DESCRIPTION
NC No Connect
A0 - A10 Address Inputs
E Chip Enable/Power Down
VSS/GND Ground
DQ0 - DQ7 Data In/Data Out
VCC
W
Power (+5V)
Write Enable
G Output Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 2998.1




 HM-6516
Functional Diagram
HM-6516
A10
A9
A8
A7
A6
A5
A4
G
W
E
A
LATCHED
7
GATED
ADDRESS
REGISTER
A
ROW
DECODER 128
7
LG
G
128 x 128
MATRIX
16 16 16 16 16 16 16 16
GATED COLUMN
DECODER
8
44
AA
L LATCHED ADDRESS
REGISTER
A3 A2 A1 A0
1 OF 8
A
A
DQ0
8 THRU
DQ7
6-2




 HM-6516
HM-6516
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input or Output Voltage Applied for all Grades . . . . . . .GND -0.3V to
VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Thermal Resistance
θJA
CERDIP Package . . . . . . . . . . . . . . . . 48oC/W
θJC
8oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W
12oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Ranges:
HM-6516B-9, HM-6516-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25953 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6516B-9, HM-6516-9)
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
ICCSB Standby Supply Current
- 50 µA IO = 0mA, VI = VCC or GND,
VCC = 5.5V, HM-6516B-9
- 100 µA IO = 0mA, VI = VCC or GND,
HM-6516-9
ICCOP Operating Supply Current (Note 1)
ICCDR Data Retention Supply Current
VCCDR Data Retention Supply Voltage
- 10 mA f = 1MHz, IO = 0mA, G = VCC, VCC =
5.5V, VI = VCC or GND
- 25 µA VCC = 2.0V, IO = 0mA, VI = VCC or
GND, E = VCC, HM-6516B-9
- 50 µA VCC = 2.0V, IO = 0mA, VI = VCC or
GND, E = VCC, HM-6516-9
2.0 -
V
II
IIOZ
VIL
VIH
VOL
VOH1
VOH2
Input Leakage Current
Input/Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage (Note 2)
-1.0 +1.0
-1.0 +1.0
-0.3 0.8
2.4 VCC +0.3
- 0.4
2.4 -
VCC -0.4
-
µA VI = VCC or GND, VCC = 5.5V
µA VIO = VCC or GND, VCC = 5.5V
V VCC = 4.5V
V VCC = 5.5V
V IO = 3.2mA, VCC = 4.5V
V IO = -1.0mA, VCC = 4.5V
V IO = -100µA, VCC = 4.5V
Capacitance TA = +25oC
SYMBOL
PARAMETER
CI Input Capacitance (Note 2)
CIO Input/Output Capacitance (Note 2)
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
MAX
8
10
UNITS
pF
pF
TEST CONDITIONS
f = 1MHz, All measurements are
referenced to device GND
6-3



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