||HM5257165B-75/A6 HM5257805B-75/A6 HM5257405B-75/A6
512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM
E0081H10 (1st edition) (Previous ADE-203-1237A (Z)) Jan. 31, 2001 Description
The HM5257165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5257805B is a 512-Mbit SDRAM organized as 16777216-word × 8-bit × 4 bank. The HM5257405B is a 512-Mbit SDRAM organized as 33554432-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packag.