Multiplier Accumulator. HMA510GM-75883 Datasheet

HMA510GM-75883 Accumulator. Datasheet pdf. Equivalent

HMA510GM-75883 Datasheet
Recommendation HMA510GM-75883 Datasheet
Part HMA510GM-75883
Description 16 x 16-Bit CMOS Parallel Multiplier Accumulator
Feature HMA510GM-75883; HMA510/883 April 1997 16 x 16-Bit CMOS Parallel Multiplier Accumulator Description The HMA510/883 i.
Manufacture Intersil Corporation
Datasheet
Download HMA510GM-75883 Datasheet




Intersil Corporation HMA510GM-75883
HMA510/883
April 1997
16 x 16-Bit CMOS Parallel
Multiplier Accumulator
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 16 x 16-Bit Parallel Multiplication with Accumulation
to a 35-Bit Result
• High-Speed (55ns) Multiply Accumulate Time
• Low Power CMOS Operation
- ICCSB = 500µA Maximum
- ICCOP = 7.0mA Maximum at 1.0MHz
• HMA510/883 is Compatible with the CY7C510 and the
IDT7210
• Supports Two’s Complement or Unsigned Magnitude
Operations
• Three-State Outputs
Ordering Information
PART NUMBER
HMA510GM-55/883
HMA510GM-65/883
HMA510GM-75/883
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 68 Ld CPGA
-55 to 125 68 Ld CPGA
-55 to 125 68 Ld CPGA
PKG.
NO.
G68.B
G68.B
G68.B
Description
The HMA510/883 is a high speed, low power CMOS 16 x
16-bit parallel multiplier accumulator capable of operating at
55ns clocked multiply-accumulate cycles. The 16-bit X and Y
operands may be specified as either two’s complement or
unsigned magnitude format. Additional inputs are provided
for the accumulator functions which include: loading the
accumulator with the current product, adding or subtracting
the accumulator contents and the current product, and pre-
loading the Accumulator Registers from the external inputs.
All inputs and outputs are registered. The registers are all
positive edge triggered, and are latched on the rising edge of
the associated clock signal. The 35-bit Accumulator Output
Register is broken into three parts. The 16-bit least signifi-
cant product (LSP), the 16-bit most significant product
(MSP), and the 3-bit extended product (XTP) Registers. The
XTP and MSP Registers have dedicated output ports, while
the LSP Register shares the Y-inputs in a multiplexed fash-
ion. The entire 35-bit Accumulator Output Register may be
preloaded at any time through the use of the bidirectional
output ports and the preloaded control.
Block Diagram
X0-15
16
RND SUB Y0-15 P0-15
TC ACC
16
PRELOAD
CLKP
REGISTER
REGISTER
REGISTER
CLKY
CLKX
XTP REGISTER
MULTIPLIER ARRAY
35
ACCUMULATOR
MSP REGISTER LSP REGISTER
3 16
35
16
OEX
OEM
OEL
P32-34
P16-31
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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File Number 2807.2



Intersil Corporation HMA510GM-75883
HMA510/883
Pinout
68 LEAD CPGA
TOP VIEW
11 N/C X15 RND ACC CLKY TC PREL CLKP P33
10 X13 X14 OEL SUB CLKX VCC OEX OEM P34 P32 N/C
9 X11 X12
P30 P31
8 X9 X10
P28 P29
7 X7
X8
6 X5
X6
TOP VIEW
P26 P27
P24 P25
5 X3
X4
P22 P23
4 X1
X2
P20 P21
3 Y0/P0 X0
P18 P19
2
N/C
Y1/P1 Y3/P3 Y5/P5 Y7/P7 Y8/P8
Y10/
P10
Y12/
P12
Y14/
P14
P16
P17
1
Y2/P2 Y4/P4 Y6/P6
GND Y9/P9
Y11/
P11
Y13/
P13
Y15/
P15
N/C
Pin Descriptions
A B CD E F GH J K L
NAME
TYPE
DESCRIPTION
VCC
GND
The +5V power supply pins. 0.1µF capacitors between the VCC and GND pins are recommended.
The device ground.
X0-X15
I X-Input Data. These 16 data inputs provide the multiplicand which may be in two's complement or
unsigned magnitude format.
Y0-Y15/P0-P15
I/O Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which may be in two's com-
plement or unsigned magnitude format. It may also be used for output of the least significant product
(P0-P15) or for preloading the LSP Register.
P16-P3
I/O MSP Output Data. This 16-bit port is used to provide the most significant product output (P16-P31).
It may also be used to preload the MSP Register.
P32-P34
I/O XTP Output Data. This 3-bit port is used to provide the extended product output (P32-P34). It may
also be used to preload the XTP Register.
TC I Two's Complement Control. Input data is interpreted as two's complement when this control is HIGH.
A LOW indicates the data is to be interpreted as unsigned magnitude format. This control is latched
on the rising edge of CLKX or CLKY.
ACC
I Accumulate Control. When this control is HIGH, the Accumulator Output Register contents are added
to or subtracted from the current product, and the result is stored back into the Accumulator Output
Register.
When LOW, the product is loaded into the Accumulator Output Register overwriting the current con-
tents. This control is also latched on the rising edge of CLKX or CLKY.
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Intersil Corporation HMA510GM-75883
HMA510/883
Pin Descriptions (Continued)
NAME
TYPE
DESCRIPTION
SUB
I Subtract Control. When both SUB and ACC are HIGH, the Accumulator Register contents are sub-
tracted from the current product. When ACC is HIGH and SUB is LOW, the Accumulator Register
contents and the current product are summed. The SUB control input is latched on the rising edge of
CLKX or CLKY.
RND
I Round Control. When this control is HIGH, a one is added to the most significant bit of the LSP. When
LOW, the product is unchanged.
PREL
I Preload Control. When this control is HIGH, the three bidirectional ports may be used to preload the
Accumulator Registers. The three-state controls (OEX, OEM, OEL) must be HIGH, and the data will
be preloaded on the rising edge of CLKP. When this control is LOW, the Accumulator Registers func-
tion in a normal manner.
OEL
I Y-Input/LSP Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high
impedance state. This state is required for Y-data input or preloading the LSP Register. When OEL
is LOW, the port is enabled for LSP output.
OEM
I MSP Output Port Three-State Control. A LOW on this control line enables the port for output. When
OEM is HIGH, the output drivers are in the high impedance state.
This control must be HIGH for preloading the MSP Register.
OEX
I XTP Output Port Three-State Control. A LOW on this control line enables the port for output. When
OEX is HIGH, the output drivers are in the high impedance state. This control must be HIGH for pre-
loading the XTP Register.
CLKX
I X-Register Clock. The rising edge of this clock latches the X-Data Input Register along with the TC,
ACC, SUB and RND inputs.
CLKY
I Y-Register Clock. The rising edge of this clock latches the Y-Data Input Register along with the TC,
ACC, SUB and RND inputs.
CLKP
I Product Register Clock. The rising edge of CLKP latches the LSP, MSP and XTP Registers. If the
preload control is active, the data on the I/O ports is loaded into these registers. If preload is not ac-
tive, the accumulated product is loaded into the registers.
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