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Chip Microcomputer. CXP5080 Datasheet |
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CXP5080
CMOS 4-bit Single Chip Microcomputer
Piggyback/
evaluator type
For the availability of this product, please contact the sales office.
Description
CXP5080 is a CMOS 4-bit single chip microcomputer
64 pin PSDIP (Ceramic) 64 pin PQFP (Ceramic)
of piggyback/evaluator combined type which has
been developed for functional evaluation of the
CXP5084/5086.
Features
• Instruction cycle 3.8µs/4.19MHz (CXP5080)
1.9µs/4.19MHz (CXP5080H)
• ROM capacity
Maximum 8K bytes (EPROM 27C64, LCC/DIP type 27C64)
• RAM capacity
400 × 4 bits (Including stack, display area)
• 32 general purpose I/O ports
• 16 large current output ports
• LCD controller/driver (Enables to direct drive)
— Enables to specify the segment output of 24, 20 and 16 optionally
— Enables to select program of the duty, 1/2, 1/3 and 1/4
— 1/3 bias
• 2 external interruption input pins
• 8-bit timer, 8-bit timer/event counter and 18-bit time base timer, independently controlled
• Arithmetic and logical operations possible between the entire RAM area, l/O area and the accumulator by
means of memory mapped I/O
• Reference to the entire ROM area is possible with the table look-up instruction
• 2 kinds of power down modes of sleep and stop
• Power on reset circuit (mask option)
• The oscillation circuit may be optionally specified as the crystal oscillation type or the CR oscillation type
• 64-pin ceramic SDIP/QFP
Note) Mask options are determined according to the CXP5080 category.
For details refer to the product list.
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E61113A7Z-PS
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Block Diagram
(Enables to specify
the I/O with bit unit)
Port A
Port B
(Enables to specify
the I/O with port unit)
44
Port C
Port D
(Combined use of mask
with segment output, optional.)
44
Port E
Port F
CXP5080
Register
400 × 4
bits
Data memory
Stack
Data memory
ALU
Accumulator
Flag
Timer (8)
Timer/counter (8)
Serial I/O (8)
Interruption control
Program
counter (13)
Address buffer
13
A0 to A12
I0 to I7
8
Instruction
input buffer
VL
VLC1
VLC2
VLC3
LCD
controller/driver
8 16 4
SEG16 SEG0 COM0
to to to
SEG23 SEG15 COM3
Port X
Port Y
Instruction control
Time base timer (18)
Clock control
EXTAL
XTAL
(Combined use of serial I/O)
–2–
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Pin Assignment 1 (Top View) 64 pin PSDIP Package
VL
XTAL
EXTAL
RST
WP
INT1
PY0
PY1
PY2/INT2
PY3/EC
PX0/SC
PX1/SOB
PX2/SOA
PX3/SI
PD0
PD1
PD2
PD3
PC0
PC1
PC2
PC3
PB0
PB1
PB2
PB3
PA0
PA1
PA2
PA3
PESEL
VSS
1 64
2 63
3 62
4 61
5 60
6 59
1 VDD
VDD 28
7 58
2 A12
VDD 27
8 57
3 A7
VDD 26
9 56
4 A6
A8 25
10 55
5 A5
A9 24
11 54
6 A4
A11 23
12 53
7 A3
VSS 22
13 52
8 A2
A10 21
14
9 A1
VSS 20
51
15 50
10 A0
I7 19
16 49
11 I0
I6 18
17 48
12 I1
I5 17
18
13 I2
I4 16
47
19
14 VSS
I3 15
46
20 45
21 44
22 43
23 42
24 41
25 40
26 39
27 38
28 37
29 36
30 35
31 34
32 33
VDD
VLC3
VLC2
VLC1
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16/PF0
SEG17/PF1
SEG18/PF2
SEG19/PF3
SEG20/PE0
SEG21/PE1
SEG22/PE2
SEG23/PE3
CXP5080
Note)
PESEL pin serves to switch the I/O signal of the socket on top of the package from interface with the
evaluator (Eva mode) to interface with EPROM (Piggyback mode).
Setting PESEL pin to H Ievel brings Eva mode to enable the connection with the evaluator. Setting it to
L level brings piggyback mode to enable the mounting of EPROM. For QFP piggyback, it is necessary
only to exchange EVACAP (or EPROM) for EPROM (or EVACAP) and no other special measures are
required.
–3–
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