VersatileI/O Control. AM29LV642D Datasheet

AM29LV642D Control. Datasheet pdf. Equivalent

AM29LV642D Datasheet
Recommendation AM29LV642D Datasheet
Part AM29LV642D
Description 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
Feature AM29LV642D; Am29LV642D Data Sheet July 2003 The following document specifies Spansion memory products that are .
Manufacture Advanced Micro Devices
Download AM29LV642D Datasheet

Advanced Micro Devices AM29LV642D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 25022 Revision A Amendment 0 Issue Date August 14, 2001

Advanced Micro Devices AM29LV642D
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/OControl
s Two 64 Megabit (Am29LV640D) in a single 64-ball 13
x 11 mm Fortified BGA package (Note: Features will
be described for each internal Am29LV640D)
s Two Chip Enable pins
Two CE# pins to control selection of each internal
Am29LV640D devices
s Single power supply operation
3.0 to 3.6 volt read, erase, and program operations
s VersatileI/Ocontrol
Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the VIO pin
s High performance
Access times as fast as 90 ns
s Manufactured on 0.23 µm process technology
s CFI (Common Flash Interface) compliant
Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
s Ultra low power consumption (typical values at 3.0 V,
5 MHz) for the part
9 mA typical active read current
26 mA typical erase/program current
400 nA typical standby mode current
s Flexible sector architecture
Two hundred fifty-six 32 Kword sectors
s Sector Protection
A hardware method to lock a sector to prevent
program or erase operations within that sector
Sectors can be locked in-system or via programming
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s Embedded Algorithms
Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
Embedded Program algorithm automatically writes
and verifies data at specified addresses
s Compatibility with JEDEC standards
Except for the additional CE2# pin, the Fortified BGA
is pinout and software compatible with single-power
supply Flash
Superior inadvertent write protection
s Minimum 1 million erase cycle guarantee per sector
s 64-ball Fortified BGA Package
s Erase Suspend/Erase Resume
Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
s Data# Polling and toggle bits
Provides a software method of detecting program or
erase operation completion
s Unlock Bypass Program command
Reduces overall programming time when issuing
multiple program command sequences
s Ready/Busy# pin (RY/BY#)
Provides a hardware method of detecting program or
erase cycle completion
s Hardware reset pin (RESET#)
Hardware method to reset the device for reading array
s ACC pin
Accelerates programming time for higher throughput
during system production
s Program and Erase Performance (VHH not applied to
the ACC input pin)
Word program time: 11 µs typical
Sector erase time: 1.6 s typical for each 32 Kword
s 20-year data retention at 125°C
Reliable operation for the life of the system
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 25022 Rev: A Amendment/0
Issue Date: August 14, 2001
Refer to AMD’s Website ( for the latest information.

Advanced Micro Devices AM29LV642D
The Am29LV642D is a 128 Mbit, 3.0 Volt (3.0 V to 3.6
V) single power supply flash memory device organized
as two Am29LV640D dice in a single 64-ball Fortified
BGA package. Each Am29LV640D is a 64 Mbit, 3.0
Volt (3.0 V to 3.6 V) single power supply flash memory
device organized as 4,194,304 words. Data appears
on DQ0-DQ15. The device is designed to be pro-
grammed in-system with the standard system 3.0 volt
VCC supply. A 12.0 volt VPP is not required for program
or erase operations. The Am29LV642D is equipped
with two CE# pins for flexible selection between the
two internal 64 Mb devices. The device can also be
programmed in standard EPROM programmers.
The Am29LV642D offers access times of 90 and 120
ns and is offered in a 64-ball Fortified BGA package.
To eliminate bus contention the Am29LV642D device
has two separate chip enables (CE# and CE2#). Each
chip enable (CE# or CE2#) is connected to only one of
the two dice in the Am29LV642D package. To the
system, this device will be the same as two inde-
pendent Am29LV640D on the same board. The
only difference is that they are now packaged to-
gether to reduce board space.
Each device requires only a single 3.0 Volt power
supply (3.0 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithman internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithman internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The VersatileI/O™ (VIO) control allows the host sys-
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its
data inputs to the same voltage level that is asserted
on the VIO pin. This allows the device to operate in 1.8
V, 3 V, or 5 V system environment as required. For
voltage levels below 3 V, contact an AMD representa-
tive for more information.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
gle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to VHH, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
AMDs Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
2 Am29LV642D

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