edge-triggered flip-flops. 74F109 Datasheet

74F109 flip-flops. Datasheet pdf. Equivalent


NXP 74F109
INTEGRATED CIRCUITS
74F109
Positive J-K positive edge-triggered
flip-flops
Product specification
IC15 Data Handbook
1990 Oct 23
Philips
Semiconductors


74F109 Datasheet
Recommendation 74F109 Datasheet
Part 74F109
Description Positive J-K positive edge-triggered flip-flops
Feature 74F109; INTEGRATED CIRCUITS 74F109 Positive J-K positive edge-triggered flip-flops Product specification IC.
Manufacture NXP
Datasheet
Download 74F109 Datasheet




NXP 74F109
Philips Semiconductors
Postive J-K positive edge-triggered flip-flops
Product specification
74F109
FEATURE
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F109 is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock (CP) input.
The J and K are edge-triggered inputs which control the state
changes of the flip-flops as described in the function table. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. The J and K inputs must
be stable just one setup time prior to the low-to-high transition of the
clock for predictable operation. The JK design allows operation as a
D flip-flop by tying J and K inputs together. Although the clock input
is level sensitive, the positive transition of the clock pulse between
the 0.8V and 2.0V levels should be equal to or less than the clock to
output delay time for reliable operation.
PIN CONFIGURATION
RD0 1
J0 2
K0 3
CP0 4
SD0 5
Q0 6
Q0 7
GND 8
16 VCC
15 RD1
14 J1
13 K1
12 CP1
11 SD1
10 Q1
9 Q1
SF00135
TYPE
74F109
TYPICAL fmax
125MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
12.3mA
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F109N
INDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = –40°C to +85°C
I74F109N
16-pin plastic SO
N74F109D
I74F109D
PKG DWG #
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
J0, J1
J inputs
1.0/1.0
K0, K1
K inputs
1.0/1.0
CP0, CP1
Clock inputs (active rising edge)
1.0/1.0
SD0, SD1
Set inputs (active Low)
1.0/3.0
RD0, RD1
Reset inputs (active Low)
1.0/3.0
Q0, Q1, Q0, Q1
Data outputs
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
4
5
1
12
11
15
VCC = Pin 16
GND = Pin 8
2 14 3 13
CP0 J0 J1 K0 K1
SD0
RD0
CP1
SD1
RD1 Q0 Q0 Q1 Q1
6 7 10 9
SF00136
2 1J
4 C1
3 1K
1R
5S
14 2J
12 C2
13 2K
15 R
11 S
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
1.0mA/20mA
6
7
10
9
SF00137
October 23, 1990
2
853–0337 00783



NXP 74F109
Philips Semiconductors
Postive J-K positive edge-triggered flip-flops
Product specification
74F109
LOGIC DIAGRAM
Q 7, 9
3, 13
K
2, 14
J
4, 12
CP
5, 11
SD
1, 15
RD
VCC = Pin 16
GND = Pin 8
6, 10
Q
SF00138
FUNCTION TABLE
INPUTS
SD RD CP J
OUTPUTS
OPERATING MODE
KQQ
L H X X X H L Asynchronous set
H L X X X L H Asynchronous reset
L L X X X H H Undetermined*
H H X X q q Hold
H H h l q q Toggle
H H h h H L Load ”1” (set)
H H l l L H Load ”0” (reset)
H H l h q q Hold ’no change”
NOTES:
H = High-voltage level
h = High-voltage level one setup time prior to low-to-high
clock transition
L = Low-voltage level
l = Low-voltage level one setup time prior to low-to-high
clock transition
q = Lower case indicate the state of the referenced output
prior to the low-to-high clock transition
X = Don’t care
= Low-to-high clock transition
= Not low-to-high clock transition
* = Both outputs will be high if both SD and RD go low
simultaneously
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
VCC
VIN
IIN
VOUT
IOUT
Tamb
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Commercial range
Industrial range
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to VCC
40
0 to +70
–40 to +85
V
V
mA
V
mA
°C
°C
Tstg Storage temperature range
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC Supply voltage
VIN High-level input voltage
VIL Low-level input voltage
IIK Input clamp current
IOH High-level output current
IOL Low-level output current
Tamb
Operating free-air temperature range
Commercial range
Industrial range
LIMITS
MIN
NOM
MAX
4.5 5.0 5.5
2.0
0.8
–18
–1
20
0 +70
–40 +85
UNIT
V
V
V
mA
mA
mA
°C
°C
October 23, 1990
3







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