74126 Buffer Datasheet

74126 Datasheet, PDF, Equivalent


Part Number

74126

Description

Quad 3-STATE Buffer

Manufacture

Fairchild Semiconductor

Total Page 4 Pages
Datasheet
Download 74126 Datasheet


74126
August 1986
Revised March 2000
DM74LS126A
Quad 3-STATE Buffer
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the 3-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned OFF presenting a high-imped-
ance state to the bus line. Thus the output will act neither
as a significant load nor as a driver. To minimize the possi-
bility that two outputs will attempt to take a common bus to
opposite logic levels, the disable time is shorter than the
enable time of the outputs.
Ordering Code:
Order Number Package Number
Package Description
DM74LS126AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS126AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y=A
Inputs
AC
LH
HH
XL
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
Hi-Z = 3-STATE (Outputs are disabled)
Output
Y
L
H
Hi-Z
© 2000 Fairchild Semiconductor Corporation DS006388
www.fairchildsemi.com

74126
Absolute Maximum Ratings(Note 1)
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range
65°C to +150°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
TA
Parameter
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free Air Operating Temperature
Min
4.75
Nom
5
Max
5.25
0.8
2.6
24
0 70
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI Input Clamp Voltage
VCC = Min, II = −18 mA
VOH HIGH Level
Output Voltage
VCC = Min, IOH = Max
VIH = Min
2.4
VOL LOW Level
VCC = Min, IOL = Max
Output Voltage
VIL = Max, VIH = Min
IOL = 12 mA, VCC = Min
II
Input Current @ Max Input Voltage
VCC = Max, VI = 7V
IIH HIGH Level Input Current
VCC = Max, VI = 2.7V
IIL LOW Level Input Current
VCC = Max, VI = 0.4V
IOZH
Off-State Output Current with
VCC = Max, VO = 2.4V
HIGH Level Output Voltage Applied
VIH = Min, VIL = Max
IOZL Off-State Output Current with
VCC = Max, VO = 0.4V
LOW Level Output Voltage Applied
VIH = Min, VIL = Max
IOS Short Circuit Output Current
VCC = Max (Note 3)
20
ICC Supply Current
VCC = Max
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Typ
(Note 2)
Max
1.5
0.35
0.25
12
0.5
0.4
0.1
20
0.4
20
20
100
22
Switching Characteristics
VCC = 5V, TA = 25°C
Symbol
Parameter
tPLH Propagation Delay Time LOW-to-HIGH Level Output
tPHL Propagation Delay Time HIGH-to-LOW Level Output
tPZH Output Enable Time to HIGH Level Output
tPZL Output Enable Time to LOW Level Output
tPHZ Output Disable Time from HIGH Level Output (Note 4)
tPLZ Output Disable Time from LOW Level Output (Note 4)
Note 4: CL = 5pF.
RL = 667
CL = 50 pF
CL = 150 pF
Min Max Min Max
15 21
18 22
30 36
30 42
25
25
Units
V
V
V
mA
mA
°C
Units
V
V
V
mA
µA
mA
µA
µA
mA
mA
Units
ns
ns
ns
ns
ns
ns
www.fairchildsemi.com
2


Features DM74LS126A Quad 3-STATE Buffer August 1 986 Revised March 2000 DM74LS126A Quad 3-STATE Buffer General Description Thi s device contains four independent gate s each of which performs a non-invertin g buffer function. The outputs have the 3-STATE feature. When enabled, the out puts exhibit the low impedance characte ristics of a standard LS output with ad ditional drive capability to permit the driving of bus lines without external resistors. When disabled, both the outp ut transistors are turned OFF presentin g a high-impedance state to the bus lin e. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outpu ts will attempt to take a common bus to opposite logic levels, the disable tim e is shorter than the enable time of th e outputs. Ordering Code: Order Number DM74LS126AM DM74LS126AN Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC) , JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Packa.
Keywords 74126, datasheet, pdf, Fairchild Semiconductor, Quad, 3-STATE, Buffer, 4126, 126, 26, 7412, 741, 74, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)