X88257 Micro-Peripheral Datasheet

X88257 Datasheet, PDF, Equivalent


Part Number

X88257

Description

E2 Micro-Peripheral

Manufacture

Xicor

Total Page 15 Pages
Datasheet
Download X88257 Datasheet


X88257
8X0858125M7icrocontroller Family Compatible
256K
X88257
32,768 x 8 Bit
E2 Micro-Peripheral
FEATURES
• Multiplexed Address/Data Bus
—Direct Interface to Popular 8051 Family
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Active Maximum
—500µA Standby Maximum
• Software Data Protection
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 128 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
• 28-Lead PDIP Package
• 28-Lead SOIC Package
• 32-Lead PLCC Package
DESCRIPTION
The X88257 is an 32K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X88257 features a multiplexed address and
data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
FUNCTIONAL DIAGRAM
CE, CE
WR
RD
PSEN
A8–A14
ALE
CONTROL
LOGIC
LX
AD
TE
CC
HO
ED
SE
SOFTWARE
DATA
PROTECT
32K x 8
E2PROM
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
6509 ILL F02.1
© Xicor, Inc. 1994-1997 Patents Pending
6509-1.9 4/9/96 T2/C5/D8 NS
1 Characteristics subject to change without notice

X88257
X88257
PIN DESCRIPTIONS
Address/Data (A/D0–A/D7)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while ALE is HIGH. After
ALE transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on RD, WR, PSEN,
and CE.
Addresses (A8–A14)
High order addresses flow into the device when ALE =
VIH and are latched when ALE goes LOW.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, ALE is LOW, and
CE is LOW, the X88257 is placed in the low power
standby mode. If CE is used to select the device, the CE
must be tied LOW.
Chip Enable (CE)
Chip enable is active HIGH. When CE is used to select
the device, the CE must be tied HIGH.
Program Store Enable (PSEN)
When the X88257 is to be used in a 8051-based system,
PSEN is tied directly to the microcontroller’s PSEN
output.
Read (RD)
When the X88257 is to be used in a 8051-based system,
RD is tied directly to the microcontroller’s RD output.
Write (WR)
When the X88257 is to be used in a 8051-based system,
WR is tied directly to the microcontroller’s WR output.
Address Latch Enable (ALE)
Addresses flow through the latches to address decoders
when ALE is HIGH and are latched when ALE transitions
from a HIGH to LOW.
PIN CONFIGURATION
PDIP
SOIC
A14
A12
ALE
PSEN
CE
NC
NC
NC
NC
NC
A/D0
A/D1
A/D2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 X88257 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
PLCC
VCC
WR
A13
A8
A9
A11
RD
A10
CE
A/D7
A/D6
A/D5
A/D4
A/D3
6509 FHD F01.3
PSEN
CE
NC
NC
NC
NC
NC
NC
A/D0
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9
X88257
25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
A8
A9
A11
NC
RD
A10
CE
A/D7
A/D6
PIN NAMES
Symbol
ALE
A/D0–A/D7
A8–A14
RD
WR
PSEN
CE, CE
VSS
VCC
NC
6509 FHD F01A.5
Description
Address Latch Enable
Address Inputs/Data I/O
Address Inputs
Read Input
Write Input
Program Store Enable Input
Chip Enable
Ground
Supply Voltage
No Connect
6509 PGM T01.1
2


Features X88257 8051 Microcontroller Family Compa tible 256K X88257 E2 Micro-Peripheral DESCRIPTION 32,768 x 8 Bit FEATURES Multiplexed Address/Data Bus —Dire ct Interface to Popular 8051 Family • High Performance CMOS —Fast Access T ime, 120ns —Low Power —60mA Active Maximum —500µA Standby Maximum • S oftware Data Protection • Toggle Bit Polling —Early End of Write Detection • Page Mode Write —Allows up to 12 8 Bytes to be Written in One Write Cycl e • High Reliability —Endurance: 10 ,000 Write Cycle —Data Retention: 100 Years • 28-Lead PDIP Package • 28- Lead SOIC Package • 32-Lead PLCC Pack age The X88257 is an 32K x 8 E2PROM fa bricated with advanced CMOS Textured Po ly Floating Gate Technology. The X88257 features a multiplexed address and dat a bus allowing direct interface to a va riety of popular single-chip microcontr ollers operating in expanded multiplexe d mode without the need for additional interface circuitry. FUNCTIONAL DIAGRAM CE, CE WR RD PSEN A8–A14 CONTROL LOGIC X D E C O D E SOFTW.
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