X25128 Datasheet: SPI Serial E 2 PROM with Block Lock TM Protection





X25128 SPI Serial E 2 PROM with Block Lock TM Protection Datasheet

Part Number X25128
Description SPI Serial E 2 PROM with Block Lock TM Protection
Manufacture Xicor
Total Page 15 Pages
PDF Download Download X25128 Datasheet PDF

Features: APPLICATION NOTE A VA I L A B L E AN61 128K X25128 SPI Serial E2PROM with Blo ck LockTM Protection DESCRIPTION 16K x 8 Bit FEATURES • • • • • • • • • • • 2MHz Cloc k Rate SPI Modes (0,0 & 1,1) 16K X 8 Bi ts —32 Byte Page Mode Low Power CMOS —<1µ A Standby Current —<5mA Activ e Current 2.7V To 5.5V Power Supply Blo ck Lock Protection —Protect 1/4, 1/2 or all of E2PROM Array Built-in Inadver tent Write Protection —Power-Up/Power -Down protection circuitry —Write Ena ble Latch —Write Protect Pin Self-Tim ed Write Cycle —5ms Write Cycle Time (Typical) High Reliability —Endurance : 100,000 cycles —Data Retention: 100 Years —ESD protection: 2000V on all pins 14-Lead SOIC Package 16-Lead SOIC Package 8-Lead PDIP Package FUNCTIONAL DIAGRAM STATUS REGISTER WRITE PROTECT L OGIC The X25128 is a CMOS 131,072-bit serial E2PROM, internally organized as 16K x 8. The X25128 features a Serial P eripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals.

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APPLICATION NOTE
A VA I L A B L E
AN61
128K
X25128
SPI Serial E2PROM with Block LockTM Protection
16K x 8 Bit
FEATURES
2MHz Clock Rate
SPI Modes (0,0 & 1,1)
16K X 8 Bits
—32 Byte Page Mode
Low Power CMOS
—<1µA Standby Current
—<5mA Active Current
2.7V To 5.5V Power Supply
Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
14-Lead SOIC Package
16-Lead SOIC Package
8-Lead PDIP Package
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
DESCRIPTION
The X25128 is a CMOS 131,072-bit serial E2PROM,
internally organized as 16K x 8. The X25128 features
a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate
data in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
The X25128 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25128 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25128 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25128 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
128
128
256
16K BYTE
ARRAY
16 X 256
16 X 256
32 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
32 8
Y DECODE
DATA REGISTER
3091 FM F01
©Xicor Inc. 1994, 1995, 1996 Patents Pending
3091-2.9 5/14/97 T2/C0/D2 SH
Characteristics subject to change without notice
1

                    
                    






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