X40620 EEPROM Datasheet

X40620 Datasheet, PDF, Equivalent


Part Number

X40620

Description

Dual Voltage CPU Supervisor with 64K Serial EEPROM

Manufacture

Xicor

Total Page 17 Pages
Datasheet
Download X40620 Datasheet


X40620
64K X40620
Dual Voltage CPU Supervisor with 64K Serial EEPROM
FEATURES
• Dual Voltage Detection and Reset Assertion
—Three standard reset threshold settings. (3.1V/
2.6V, 3.1V/1.7V, 2.9V/2.3V)
—Adjust low voltage reset threshold voltages
using special programming sequence
—RESET signal valid down to VCC=1V
• Watchdog Timer (150ms)
• Power On Reset (150ms)
• Low Power CMOS
—10µA typical standby current, watchdog on
—400µA typical standby current, watchdog off
• 64kbit 2-Wire Serial EEPROM
—1MHz serial interface speed
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.5 to 3.7V Power Supply Operation
• 8-Lead TSSOP package
DESCRIPTION
The X40620 combines several functions into one
device. The first is a dual voltage monitoring, power-on
reset control, watchdog timer and 64Kbit serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET active for a period of time.
This allows the power supply and system oscillator to
stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the set minimum Vtrip point. RESET is
active until VCC returns to proper operating level and
stabilizes.
A second voltage monitor circuit (V2MON) tracks the
unregulated supply to provide a power fail warning or
monitors different power supply voltage. When the
second monitored voltage drops below a preset
V2TRIP voltage. V2FAIL is active until V2 returns to
proper operating level and above the V2TRIP voltage.
Five common low voltage combinations are available,
however, Xicor’s unique circuits allows the threshold
for either voltage monitor to be reprogrammed to meet
special needs or to fine-tune the threshold for applica-
tions requiring higher precision.
BLOCK DIAGRAM
WP
Write Control
Logic
SCL
SDA
Command
Decode
and
Control
Logic
HV Generation
Timing and Control
EEPROM Array
(64Kbits)
(VCC) Control Signal
Y Decoder
Data Register
Xicor, Inc. 2000 Patents Pending
9900-3003.5 4/24/00 EP
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET
+
- V2TRIP
+
- VTRIP
V2FAIL
V2MON
VCC
Characteristics subject to change without notice. 1 of 17

X40620
X40620
PACKAGE/PINOUTS
VSS
WP
SDA
RESET
8L TSSOP
18
27
36
45
VCC
V2MON
SCL
V2FAIL
PIN NAMES
VSS
SDA
VCC
SCL
WP
V2MON
RESET
V2FAIL
Ground
Serial Data
Power
Serial Clock
Write Protect
Voltage monitor input
Low Voltage Detect Output
V2 Voltage Fail Output
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with other open drain or open col-
lector outputs. An open drain requires the use of a
pull-up resistor.
Write Protect (WP)
The WP pin should be tied HIGH at all time. (This WP
pin is reserved for internal factory testing only).
Reset Output (RESET)
RESET is an active LOW, open drain output which
goes active whenever VCC falls below the minimum
Vtrip sense level. It will remain active until VCC rises
above the minimum Vtrip sense level for 150ms.
RESET goes active if the Watchdog Timer is enabled
and there is no start bit before the end of the select-
able Watchdog time-out period. A serial start bit will
reset the Watchdog Timer. RESET also goes active on
power up at 1V and remains active for 150ms after the
power supply stabilizes.
V2 Voltage Fail Output (V2FAIL)
V2FAIL is an active LOW, open drain output which
goes active whenever V2MON falls below the mini-
mum V2trip sense level. It will remain active until
V2MON rises above the minimum V2MON sense level.
DEVICE OPERATION
Power On Reset
Application of power to the X40620 activates a Power
On Reset Circuit. This circuit goes active at 1V and
pulls the RESET pin active. This signal prevents the
system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscil-
lator. When VCC exceeds the device VTRIP value for
200ms (nominal) the circuit releases RESET allowing
the processor to begin executing code.
Low Voltage VCC (V1) Monitoring
During operation, the X40620 monitors the VCC level
and asserts RESET if supply voltage falls below a pre-
set minimum VTRIP. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
When the internal low voltage detect circuitry senses
that VCC is low, the following happens:
– The RESET pin goes active.
– Communication to the device is interrupted and any
command is aborted. If a serial nonvolatile store is in
progress when power fails, the circuitry does not
stop the nonvolatile store operation, but attempts to
complete the operation.
The low VCC threshold is typically set to 3.1V for a 2.5
to 3.7V operating range.
LOW VOLTAGE V2 MONITORING
The X40620 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V2TRIP. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until the VCC drops below 1V. It also remains active
until V2MON returns and exceeds V2TRIP by 0.2V
Characteristics subject to change without notice. 2 of 17


Features 64K X40620 Dual Voltage CPU Supervisor with 64K Serial EEPROM EEPROM memory in one package. This combination lowers s ystem cost, reduces board space require ments, and increases reliability. Apply ing voltage to VCC activates the power on reset circuit which holds RESET acti ve for a period of time. This allows th e power supply and system oscillator to stabilize before the processor can exe cute code. Low VCC detection circuitry protects the user’s system from low v oltage conditions, resetting the system when VCC falls below the set minimum V trip point. RESET is active until VCC r eturns to proper operating level and st abilizes. A second voltage monitor circ uit (V2MON) tracks the unregulated supp ly to provide a power fail warning or m onitors different power supply voltage. When the second monitored voltage drop s below a preset V2TRIP voltage. V2FAIL is active until V2 returns to proper o perating level and above the V2TRIP vol tage. Five common low voltage combinations are available, however.
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