Serial EEPROM. X40626 Datasheet

X40626 Datasheet PDF, Equivalent


Part Number

X40626

Description

Dual Voltage CPU Supervisor with 64K Serial EEPROM

Manufacture

Xicor

Total Page 23 Pages
PDF Download
Download X40626 Datasheet PDF


X40626 Datasheet
Preliminary Information
64K
X40626
8K x 8 Bit
Dual Voltage CPU Supervisor with 64K Serial EEPROM
FEATURES
• Dual voltage monitoring
—V2Mon operates independent of VCC
• Watchdog timer with selectable timeout intervals
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—User programmable VTRIP threshold
—Reset signal valid to VCC=1V
• Low power CMOS
—20µA max standby current, watchdog on
—1µA standby current, watchdog OFF
• 64Kbits of EEPROM
—64 byte page size
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lockprotection
• 400kHz 2-wire interface
—Slave addressing supports up to 4 devices on
the same bus
• 2.7V to 5.5V power supply operation
• Available Packages
—14-lead SOIC
—14-lead TSSOP
DESCRIPTION
The X40626 combines four popular functions, Power-on
Reset Control, Watchdog Timer, Dual Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to stabi-
lize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontrol-
ler fails to restart a timer within a selectable time-out
interval, the device activates the RESET signal. The user
selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the set minimum VCC trip
point. RESET is asserted until VCC returns to proper
BLOCK DIAGRAM
V2MON
WP
SDA
SCL
S0
S1
V2 Monitor
Logic
+
VTRIP2
-
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
64KB
EEPROM
Array
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
V2FAIL
RESET
Power on and
Low Voltage
VCC
+ Reset
VTRIP
-
Generation
REV 1.1.15 2/11/04
www.xicor.com
Characteristics subject to change without notice. 1 of 23

X40626 Datasheet
X40626
operating level and stabilizes. Four industry standard Vtrip
thresholds are available. However, Xicor’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block LockProtection. The
array is internally organized as 64 bytes per page. The
device features an 2-wire interface and software protocol
allowing operation on an I2C bus.
The device utilizes Xicor’s proprietary Direct Writecell,
providing a minimum endurance of 100,000 page write
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
14 Pin SOIC/TSSOP
NC
S0
S1
NC
RESET
NC
VSS
1
2
3
4
5
6
7
14 VCC
13 NC
12 WP
11 V2MON
10 V2FAIL
9 SCL
8 SDA
PIN FUNCTION
Pin
1, 4, 6, 13
2
3
5
Name
NC
S0
S1
RESET
7 VSS
8 SDA
9 SCL
10 V2FAIL
11 V2MON
12 WP
14 VCC
Function
No Internal Connections
Device Select Input
Device Select Input
Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC
falls below the minimum VCC sense level. It will remain active until VCC rises above the min-
imum VCC sense level for typically 200ms. RESET goes active if the Watchdog Timer is
enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time-
out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET
goes active on power up and remains active for typically 200ms after the power supply
stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has
an open drain output and may be wire ORed with other open drain or open collector outputs.
This pin requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the
Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time-out
period results in RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than
VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay
circuitry on this pin. This circuit works independently from the Low VCC reset and battery
switch circuits. Connect V2FAIL to VSS when not used.
V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL
goes LOW. This input can monitor an unregulated power supply with an external resistor
divider or can monitor a second power supply with no external components. Connect
V2MON to VSS or VCC when not used. There is no hysteresis in the V2MON comparator
circuits.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control
register.
Supply Voltage
REV 1.1.15 2/11/04
www.xicor.com
Characteristics subject to change without notice. 2 of 23


Features Datasheet pdf Preliminary Information 64K X40626 Dual Voltage CPU Supervisor with 64K Serial EEPROM DESCRIPTION 8K x 8 Bit FEATUR ES • Dual voltage monitoring —V2Mon operates independent of VCC • Watchd og timer with selectable timeout interv als • Low VCC detection and reset ass ertion —Four standard reset threshold voltages —User programmable VTRIP th reshold —Reset signal valid to VCC=1V • Low power CMOS —20µA max standb y current, watchdog on —1µA standby current, watchdog OFF • 64Kbits of EE PROM —64 byte page size • Built-in inadvertent write protection —Power-u p/power-down protection circuitry —Pr otect 0, 1/4, 1/2, all or 64, 128, 256 or 512 bytes of EEPROM array with progr ammable Block Lock™ protection • 40 0kHz 2-wire interface —Slave addressi ng supports up to 4 devices on the same bus • 2.7V to 5.5V power supply oper ation • Available Packages —14-lead SOIC —14-lead TSSOP BLOCK DIAGRAM V2 MON V2 Monitor Logic Watchdog Transition Detector WP Data Register Command Decode & Control Logic VCC Thresho.
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