X46402 EEPROM Datasheet

X46402 Datasheet, PDF, Equivalent


Part Number

X46402

Description

Dual Voltage CPU Supervisor with 64K Password Protected EEPROM

Manufacture

Xicor

Total Page 23 Pages
Datasheet
Download X46402 Datasheet


X46402
Preliminary Information
64K X46402
Dual Voltage CPU Supervisor with 64K Password Protected EEPROM
FEATURES
• Dual Voltage Detection and Reset Assertion
—Low Vcc Monitor
—Low V2MON Monitor
—Low Vcc Block of EEPROM Writes
—RESET Signal Valid down to Vcc=1V
• Selectable Watchdog Timer
—150ms, 450ms, 1s, 5s, 10s, 20s, 1min, OFF
• Volatile Flag shows Watchdog/Low Voltage Reset
• 64kbit 2-wire Serial EEPROM
—1MHz Serial Interface speed
—64-Byte Page Write Mode
• Two 64-Byte OTP memory blocks
—Requires 64-bit OTP password to write
• Adjustable size Password Protected Array
—64 Bit Read and Write Array Passwords
—Non-password protected array area
• 8 count tamper counter for invalid passwords
• Operates at 2.5-3.7V
• 8L TSSOP package
DESCRIPTION
The X46402 combines several functions into one device.
The first is a dual voltage CPU supervisor plus 64Kbit
serial EEPROM memory with password protected write
and read operations. The size of the password protected
area is selectable by 3 control bits. A Write Protect (WP)
pin in conjunction with a WPEN bit provides hardware
OTP control of the configuration of the array. Password
protected areas require 64 bit read or write passwords
prior to access. The eighth illegal password entry
(regardless of the number of correct entries) sets an OTP
tamper bit. This bit is one of the 32 bits in the Device ID.
A secondary voltage monitor circuit activates a V2FAIL
pin when the secondary supply voltage drops below a
V2trip voltage. This circuit is primarily intended to detect
the immediate loss of the battery supply.
A low Vcc voltage detect circuit activates a RESET pin
when Vcc drops below a VTRIP voltage. This signal also
blocks read or write operations.
A watchdog timer with the time period controlled by three
bits provides several possible time out periods from
150ms to 1 minute.
Functional Diagram
WP
Write Control
Password Logic
HV Generation
Timing and Control
SCL
SDA
Command
Decode
and
Control
Logic
Write Password Area
(Bytes)
(64, 128, 256, 512,
2K, 4K, All, None)
No Password Area
Control
OTP array 1
OTP array 2
Passwords
(Vcc) Control Signal
Y Decoder
Data Register
©Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending
9900-3003 5 1/11/00 CM
1
WATCHDOG
TIMER RESET
RESET &
WATCHDOG
TIMEBASE
POWER ON AND
LOW VOLTAGE
RESET
GENERATION
RESET
+
- V2TRIP
+
- VTRIP
V2FAIL
V2MON
Vcc
Characteristics subject to change without notice

X46402
X46402
Preliminary Information
PACKAGE/PINOUTS
VSS
WP
SDA
RESET
8L TSSOP
18
27
36
45
VCC
V2MON
SCL
V2FAIL
PIN NAMES
VSS
SDA
VCC
SCL
WP
V2MON
RESET
V2FAIL
Ground
Serial Data
Power
Serial Clock
Write Protect
Voltage monitor input
Low Voltage Detect Output
V2 Voltage Fail Output
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with other open drain or open collector out-
puts. An open drain requires the use of a pull-up resistor.
Write Protect (WP)
The WP pin works in conjunction with a nonvolatile
WPEN bit to “lock” the setting of the Watchdog Timer
control and the memory write protect bits.
Reset Output (RESET)
RESET is an active LOW, open drain output which goes
active whenever Vcc falls below the minimum Vtrip sense
level. It will remain active until Vcc rises above the mini-
mum Vtrip sense level for 150ms. RESET goes active if
the Watchdog Timer is enabled and there is no start bit
before the end of the selectable Watchdog time-out
period. A serial start bit will reset the Watchdog Timer.
RESET also goes active on power up at 1V and remains
active for 150ms after the power supply stabilizes.
V2 Voltage Fail Output (V2FAIL)
V2FAIL is an active LOW, open drain output which goes
active whenever V2MON falls below the minimum V2trip
sense level. It will remain active until V2MON rises above
the minimum V2MON sense level.
DEVICE OPERATION
Power On Reset
Application of power to the X46402 activates a Power On
Reset Circuit. This circuit goes active at 1V and pulls the
RESET pin active. This signal prevents the system micro-
processor from starting to operate with insufficient volt-
age or prior to stabilization of the oscillator. When Vcc
exceeds the device VTRIP value for 200ms (nominal) the
circuit releases RESET allowing the processor to begin
executing code.
Low Voltage Monitoring
During operation, the X46402 monitors the VCC and
V2MON levels and compares these with internal, preset
voltages.
When the internal low voltage detect circuitry senses that
V2MON is low, the V2FAIL pin goes active. Typically this
would be used by the processor as an interrupt to stop
the execution of the code or to do housekeeping in prep-
aration for an impending power failure.
When the internal low voltage detect circuitry senses that
Vcc is low, the following happens:
—The RESET pin goes active.
—The Flag bit in the control register is set to zero.
—Communication to the device is interrupted and any
command is aborted. If a serial nonvolatile store is in
progress when power fails, the circuitry does not stop
the nonvolatile store operation, but attempts to com-
plete the operation.
The RESET and V2FAIL signals remain active until Vcc
voltage drops below 1V. RESET remains active until Vcc
returns and exceeds VTRIP for 200ms. V2FAIL remains
active until immediately after V2MON returns and
exceeds it’s minimum voltage.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the Start bit. The microprocessor
must send a start bit periodically to prevent a RESET sig-
nal. The start bit must occur prior to the expiration of the
watchdog time-out period. The state of three nonvolatile
control bits in the Control Register determines the watch-
dog timer period. The microprocessor can change these
watchdog bits, or they may be “locked” by tying the WP
pin HIGH and setting the WPEN bit HIGH.
2


Features Preliminary Information 64K X46402 Dua l Voltage CPU Supervisor with 64K Passw ord Protected EEPROM DESCRIPTION The X4 6402 combines several functions into on e device. The first is a dual voltage CPU supervisor plus 64Kbit serial EEPRO M memory with password protected write and read operations. The size of the pa ssword protected area is selectable by 3 control bits. A Write Protect (WP) pi n in conjunction with a WPEN bit provid es hardware OTP control of the configu ration of the array. Password protected areas require 64 bit read or write pas swords prior to access. The eighth ille gal password entry (regardless of the n umber of correct entries) sets an OTP t amper bit. This bit is one of the 32 bi ts in the Device ID. A secondary voltag e monitor circuit activates a V2FAIL pi n when the secondary supply voltage dro ps below a V2trip voltage. This circuit is primarily intended to detect the im mediate loss of the battery supply. A l ow Vcc voltage detect circuit activates a RESET pin when Vcc drops .
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