Secure SerialFlash. X76F640 Datasheet

X76F640 Datasheet PDF, Equivalent


Part Number

X76F640

Description

Secure SerialFlash

Manufacture

Xicor

Total Page 17 Pages
PDF Download
Download X76F640 Datasheet PDF


X76F640 Datasheet
64K
X76F640
8Kx8+32x8
Secure SerialFlash
FEATURES
• 64-bit Password Security
—Five 64-bit Passwords for Read, Program
and Reset
• 8192 Byte+32 Byte Password Protected Arrays
—Seperate Read Passwords
—Seperate Write Passwords
—Reset Password
• Programmable Passwords
• Retry Counter Register
—Allows 8 tries before clearing of both arrays
—Password Protected Reset
• 32-bit Response to Reset (RST Input)
• 32 byte Sector Program
• 400kHz Clock Rate
• 2 wire Serial Interface
• Low Power CMOS
—2.7 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
• High Reliability Endurance:
—100,000 Write Cycles
• Data Retention: 100 years
• Available in:
—8 lead SOIC
—SmartCard Module
DESCRIPTION
The X76F640 is a Password Access Security Supervisor,
containing one 65536-bit Secure SerialFlash array and
one 256-bit Secure SerialFlash array. Access to each
memory array is controlled by two 64-bit passwords.
These passwords protect read and write operations of
the memory array. A separate RESET password is used
to reset the passwords and clear the memory arrays in
the event the read and write passwords are lost.
The X76F640 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the device
is controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X76F640 also features a synchronous response to
reset providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
The X76F640 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
Functional Diagram
CS
SCL
SDA
INTERFACE
LOGIC
RST
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7025-1.4 3/24/97 T2/C0/D1 SH
CHIP ENABLE
DATA TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY
AND PASSWORD
VERIFICATION LOGIC
RESET
RESPONSE REGISTER
1
8K BYTE
SerialFlash ARRAY
ARRAY 0
(PASSWORD PROTECTED)
32 BYTE
SerialFlash ARRAY
ARRAY 1
(PASSWORD PROTECTED)
RETRY COUNTER
7025 FM 01
Characteristics subject to change without notice

X76F640 Datasheet
X76F640
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a true three state serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During a
write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Chip Enable (CS)
When CS is high, the X76F640 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F640 will be in
standby mode. CS low enables the X76F640, placing it in
the active mode.
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F640 will output 32 bits of fixed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 11. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
DEVICE OPERATION
There are two primary modes of operation for the
X76F640; Protected READ and protected WRITE.
Protected operations must be performed with one of four
8-byte passwords.
The basic method of communication for the device is
established by first enabling the device (CS LOW), gen-
erating a start condition, then transmitting a command,
followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0’.
The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct pass-
word is accepted and a ACK polling has been performed,
can the data transfer occur.
To ensure the correct communication, RST must remain
LOW under all conditions except when running a
“Response to Reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
If the X76F640 is in a nonvolatile write cycle a “no ACK”
(SDA=High) response will be issued in response to load-
ing of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be termi-
nated and the part will reset and enter into a standby
mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
CS
SDA
SCL
RST
Vcc
Vss
NC
Description
Chip Select Input
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
No Connect
7025 FM T01
PIN CONFIGURATION
Smart Card
VSS
CS
SDA
NC
SOIC
18
27
36
45
VCC
RST
SCL
NC
VCC
RST
SCL
NC
GND
CS
SDA
NC
7025 FM 02
After each transaction is completed, the X76F640 will
reset and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a
protected array.
2


Features Datasheet pdf 64K X76F640 Secure SerialFlash DESCRIPT ION 8Kx8+32x8 FEATURES • 64-bit Pas sword Security —Five 64-bit Passwords for Read, Program and Reset • 8192 B yte+32 Byte Password Protected Arrays Seperate Read Passwords —Seperate W rite Passwords —Reset Password • Pr ogrammable Passwords • Retry Counter Register —Allows 8 tries before clear ing of both arrays —Password Protecte d Reset • 32-bit Response to Reset (R ST Input) • 32 byte Sector Program 400kHz Clock Rate • 2 wire Serial I nterface • Low Power CMOS —2.7 to 5 .5V operation —Standby current Less t han 1µ A —Active current less than 3 mA • High Reliability Endurance: — 100,000 Write Cycles • Data Retention : 100 years • Available in: —8 lead SOIC —SmartCard Module The X76F640 is a Password Access Security Superviso r, containing one 65536-bit Secure Seri alFlash array and one 256-bit Secure Se rialFlash array. Access to each memory array is controlled by two 64-bit passwords. These passwords protect read and write operations of the memory arr.
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