2ND GENERATION. TSW5070FNTR Datasheet

TSW5070FNTR Datasheet PDF, Equivalent


Part Number

TSW5070FNTR

Description

PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION

Manufacture

STMicroelectronics

Total Page 30 Pages
PDF Download
Download TSW5070FNTR Datasheet


TSW5070FNTR Datasheet
TS5070
TS5071
PROGRAMMABLE CODEC/FILTER
COMBO 2ND GENERATION
COMPLETE CODEC AND FILTER SYSTEM
INCLUDING :
– TRANSMIT AND RECEIVE PCM CHANNEL
FILTERS
µ-LAW OR A-LAW COMPANDING CODER
AND DECODER
– RECEIVE POWER AMPLIFIER DRIVES
300
– 4.096 MHz SERIAL PCM DATA (max)
PROGRAMMABLE FUNCTIONS :
– TRANSMIT GAIN : 25.4 dB RANGE, 0.1 dB
STEPS
– RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB
STEPS
– HYBRID BALANCE CANCELLATION FIL-
TER
– TIME-SLOT ASSIGNMENT: UP TO 64
SLOTS/FRAME
– 2 PORT ASSIGNMENT (TS5070)
– 6 INTERFACE LATCHES (TS5070)
– A OR µ-LAW
– ANALOG LOOPBACK
– DIGITAL LOOPBACK
DIRECT INTERFACE TO SOLID-STATE
SLICs
SIMPLIFIES TRANSFORMER SLIC, SINGLE
WINDING SECONDARY
STANDARD SERIAL CONTROL INTERFACE
80 mW OPERATING POWER (typ)
1.5mW STANDBY POWER (typ)
MEETS OR EXCEEDS ALL CCITT AND
LSSGR SPECIFICATIONS
TTL AND CMOS COMPATIBLE DIGITAL IN-
TERFACES
DESCRIPTION
The TS5070series are the second generationcom-
bined PCM CODEC and Filter devices optimized
for digital switching applications on subscriber and
trunk line cards.
Using advanced switched capacitor techniques the
TS5070 and TS5071 combine transmit bandpass
and receive lowpass channel filters with a com-
panding PCM encoder and decoder. The devices
are A-law and µ-law selectable and employ a con-
ventional serial PCM interface capable of being
clocked up to 4.096 MHz. A number of programma-
ble functions may be controlled via a serial control
port.
December 1997
DIP20 (Plastic)
ORDERING NUMBER:TS5071N
PLCC28
ORDERING NUMBERS: TS5070FN
TS5070FNTR
Channel gains are programmable over a 25.4 dB
range in each direction, and a programmable filter
is included to enable Hybrid Balancing to be ad-
justed to suit a wide range of loop impedance con-
ditions.
Both transformer and active SLIC interface circuits
with real or complex termination impedances can
be balanced by this filter, with cancellation in ex-
cess of 30 dB being readily achievable when meas-
ured across the passbandagainst standardtest ter-
mination networks.
To enable COMBO IIG to interface to the SLIC con-
trol leads, a number of programmable latches are
included ; each may be configured as either an in-
put or an output. The TS5070 provides 6 latches
and the TS5071 5 latches.
1/32

TSW5070FNTR Datasheet
TS5070 - TS5071
TS5070 PIN FUNCTIONALITY (PLCC28)
No. Name
Function
1
GND
Ground Input (+0V)
2
VFR0
Analog Output
3 VSS Supply Input (-5V)
4 NC Not Connected
5 NC Not Connected
6 IL3 Digital Input or Output defined by LDR register content
7 IL2 Digital Input or Output defined by LDR register content
8 FSR Digital input
9 DR1 Digital input sampled by BCLK falling edge
10 DR0 Digital input sampled by BCLK falling edge
11 CO Digital output (shifted out on CCLK rising edge)
12 CI Digital input (sampled on CCLK falling edge)
13
CCLK
Digital input (clock)
14 CS Digital input (chip select for CI/CO)
15 MR Digital Input
16
BCLK
Digital input (clock)
17
MCLK
Digital input
18 DX0 Digital output clocked by BCLK rising edge
19 DX1 Digital output clocked by BCLK rising edge
20
TSX0
Open drain output (pulled low by active DX0 time slot)
21
TSX1
Open drain output (pulled low by active DX1 time slot)
22 FSX Digital input
23 IL5 Digital input or output defined by LDR register content
24 IL4 Digital input or output defined by LDR register content
25 IL1 Digital input or output defined by LDR register content
26 IL0 Digital input or output defined by LDR register content
27 VCC Supply input (+5V)
28
VFXI
Analog input
TS5070 FUNCTIONAL DIAGRAM
VFXI
VCC=+5V
VSS=-5V
ENCODER
AZ
2/32
VFRO
GND
IL5
IL4
IL3
IL2
IL1
IL0
TX GAIN
HYBRID
BALANCE
FILTER
HYBAL 1
HYBAL 2
HYBAL 3
TS5070/71
TX TIME SLOT
Vref
CTL REG.
TX
REGISTER
TIME-SLOT
ASSIGNMENT
RX TIME SLOT
RX
REGISTER
RX GAIN
INTERFACE
LATCHES
LATCH DIR
LATCH CONT.
DECODER
CONTROL
INTERFACE
D94TL135
DX0
DX1
TSX0
TSX1
FSX
BCLK
FSR
DR0
DR1
MCLK
MR
CS
CCLK
CO
CI


Features Datasheet pdf TS5070 TS5071 PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION COMPLETE CODEC AND FILTER SYSTEM INCLUDING : – TRANSMIT AND RECEIVE PCM CHANNEL FILTERS – µ -LAW OR A-LAW COMPANDING CODER AND DEC ODER – RECEIVE POWER AMPLIFIER DRIVES 300 Ω – 4.096 MHz SERIAL PCM DATA (max) PROGRAMMABLE FUNCTIONS : – TRAN SMIT GAIN : 25.4 dB RANGE, 0.1 dB STEPS – RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB STEPS – HYBRID BALANCE CANCELLATIO N FILTER – TIME-SLOT ASSIGNMENT: UP T O 64 SLOTS/FRAME – 2 PORT ASSIGNMENT (TS5070) – 6 INTERFACE LATCHES (TS507 0) – A OR µ-LAW – ANALOG LOOPBACK – DIGITAL LOOPBACK DIRECT INTERFACE T O SOLID-STATE SLICs SIMPLIFIES TRANSFOR MER SLIC, SINGLE WINDING SECONDARY STAN DARD SERIAL CONTROL INTERFACE 80 mW OPE RATING POWER (typ) 1.5mW STANDBY POWER (typ) MEETS OR EXCEEDS ALL CCITT AND LS SGR SPECIFICATIONS TTL AND CMOS COMPATI BLE DIGITAL INTERFACES DESCRIPTION The TS5070series are the second generationc ombined PCM CODEC and Filter devices optimized for digital switching applications on subscrib.
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