TQ1090 Clock Buffer Datasheet

TQ1090 Datasheet, PDF, Equivalent


Part Number

TQ1090

Description

11-Output Configurable Clock Buffer

Manufacture

TriQuint Semiconductor

Total Page 10 Pages
Datasheet
Download TQ1090 Datasheet


TQ1090
TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
TQ1090
FBIN S1 REFCLK S0 GND GND GND
11 10 9 8 7 6 5
TEST 12
VDD 13
Q0 14
GND 15
Q1 16
Q2 17
VDD 18
Phase
Detector
VCO
MUX
Divide Logic
S1 S0
÷2
Output Buffers Group C
Group A
Group B
4 VDD
3 Q10
2 Q9
1 GND
28 Q8
27 Q7
26 VDD
19 20
GND Q3
21 22 23
Q4 VDD Q5
24 25
Q6 GND
TriQuint’s TQ1090 is a configurable clock buffer which generates 11
outputs, operating over a wide range of frequencies from 33 MHz to
45MHz, 65 MHz to 90 MHz and 130 MHz to 180 MHz. The outputs are
available at 1x, 2x and 4x, or at 1/2x, 1x and 2x, or at 1/4 x, 1/2 x and
1x the reference clock frequency, fREF.
When one of the Group A outputs (Q0–Q4) is used as feedback to the PLL,
all Group A outputs will be at fREF, all Group B outputs (Q5–Q8) will be at
2x fREF and all Group C outputs (Q9,Q10) will be at 4x fREF. When one of the
Group B outputs is used as feedback to the PLL, all Group A outputs will
be at 1/2 x fREF, all Group B outputs will be at fREF and all Group C outputs
will be at 2x fREF. When one of the Group C outputs is used as feedback to
the PLL, all Group A outputs will be at 1/4 x fREF, all Group B outputs will be
at 1/2 x fREF and all Group C outputs will be at fREF.
A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation.
This completely self-contained PLL requires no external capacitors or
resistors. The PLL’s Voltage-Controlled Oscillator (VCO) has a frequency
range from 260 MHz to 360 MHz. By feeding back one of the output clocks
to FBIN, the PLL continuously maintains frequency and phase synchron-
ization between the reference clock (REFCLK) and each of the outputs.
11-Output
Configurable
Clock Buffer
Features
• Wide frequency range:
33 MHz to 45 MHz
65 MHz to 90 MHz and
130 MHz to 180 MHz
• Output configurations:
four outputs at fREF
four outputs at 2x fREF
two output at 4x fREF or
five outputs at 1/2 x fREF
three outputs at fREF
two outputs at 2x fREF
• Selectable Phase Shift:
–2t, –t, 0, +t (t = 1/fvco)
• Low output-to-output skew:
150 ps (max) within a group
• Near-zero propagation delay
–350 ps ± 500 ps (max) or
–350 ps ±700 ps (max)
• TTL-compatible I/O with 30 mA
output drive
• Ideal for Power PCdesigns
• 28-pin J-lead surface-mount
package
For additional information and latest specifications, see our website: www.triquint.com
1

TQ1090
TQ1090
The phase relationship of the Group A outputs to Group
B and C are controlled by the phase-select pins S0 and
S1. The phase difference can be varied from –2t, –t, 0
or +t, where t = 1/fvco.
TriQuint’s patented output buffer design delivers a very
low output-to-output skew of 150 ps (max). The
TQ1090’s symmetrical TTL outputs are capable of
sourcing and sinking 30 mA.
Functional Description
The core of the TQ1090 is a Phase-Locked Loop (PLL)
that continuously compares the reference clock
(REFCLK) to the feedback clock (FBIN), maintaining a
zero frequency difference between the two. Since one
of the outputs is always connected to FBIN, the PLL
keeps the propagation delay between the outputs and
the reference clock within –350 ps +500 ps for the
TQ1090-MC500, and within –350 ps +700 ps for the
TQ1090-MC700.
The internal Voltage-Controlled Oscillator (VCO), has an
operating range of 260 MHz to 360 MHz, as shown in
Table 1. The combination of the VCO and the Divide
Logic enables the TQ1090 to operate between 33 MHz
and 45 MHz, 65 MHz and 90 MHz, and from 130 MHz
to 180 MHz.
The Shift Select pins, S0 and S1, control the phase
shift of the Group A outputs (Q0 – Q4), relative to the
other outputs. The user can select from four
incremental phase shifts as shown in Table 2 (Phase
Selection). The phase shift increment (t) is calculated
using the following equation, where n is the divide
mode:
t= 1
(fREF) (n)
In the test mode, the PLL is bypassed and REFCLK is
connected directly to the Divide Logic block via the
MUX, as shown in Figure 1. This mode is useful for
debug and test purposes. The test mode is outlined
in Table 3.
The maximum rise and fall time at the output pins is 1.4
ns. All outputs of the TQ1090 are TTL-compatible with
30 mA symmetric drive and a minimum VOH of 2.4 V.
Power-Up/Reset Synchronization
After power-up or reset, the PLL requires time before it
achieves synchronization lock. The maximum time
required for synchronization (TSYNC) is 500 ms.
Table 1. Frequency Mode Selection
Output
Reference Clock
␣ Output Frequency Range
Test Feedback Mode Frequency Range Group A: Q0–Q4 Group B: Q5,Q08 Group c: Q9,Q10
0
Group A
÷8
35 MHz – 45 MHz 35 MHz – 45 MHz
65 MHz – 90 MHz
130 MHz – 180 MHz
0
Group B
÷4
65 MHz – 90 MHz 35 MHz – 45 MHz
65 MHz – 90 MHz
130 MHz – 180 MHz
0
Group C
÷2
130 MHz – 180 MHz 35 MHz – 45 MHz
65 MHz – 90 MHz
130 MHz – 180 MHz
2 For additional information and latest specifications, see our website: www.triquint.com


Features T R I Q U I N T S E M I C O N D U C T O R, I N C . Figure 1. Block Dia gram FBIN 11 TQ1090 S1 10 REFCLK S0 9 8 GND 7 GND 6 GND 5 TEST 12 VDD 13 Phase Detector VCO 4 VDD 3 2 Q10 Q9 11-Output Configurable Clock Buffer F eatures Q0 14 GND 15 Q1 Q2 16 17 MU X Divide Logic ÷2 Output Buffers Group C Group A Group B 1 GND 28 27 S1 S0 Q8 Q7 VDD 18 26 VDD • Wide freque ncy range: 33 MHz to 45 MHz 65 MHz to 9 0 MHz and 130 MHz to 180 MHz • Output configurations: four outputs at fREF f our outputs at 2x fREF two output at 4x fREF or five outputs at 1/2 x fREF thr ee outputs at fREF two outputs at 2x fR EF • Selectable Phase Shift: –2t, t, 0, +t (t = 1/fvco) • Low output- to-output skew: 150 ps (max) within a g roup • Near-zero propagation delay 350 ps ± 500 ps (max) or –350 ps ± 700 ps (max) • TTL-compatible I/O wit h 30 mA output drive • Ideal for Powe r PC™ designs • 28-pin J-lead surfa ce-mount package SYSTEM TIMING PRODUCTS 19 20 21 22 23 24 25 GND Q3 Q4 VDD Q5 Q.
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