TQ2061 Clock Generator Datasheet

TQ2061 Datasheet, PDF, Equivalent


Part Number

TQ2061

Description

High-Frequency Clock Generator

Manufacture

TriQuint Semiconductor

Total Page 6 Pages
Datasheet
Download TQ2061 Datasheet


TQ2061
TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. Pinout Diagram
11 10 9 8 7 6 5
TQ2061
High-Frequency
Clock Generator
VDD 12
NC 13
TEST1 14
TEST2 15
NC 16
NC 17
GND 18
Phase
VCO
÷20
MUX
4 NC
3 NC
Control
MUX
2 NC
1 NC
28 NC
27 NC
26
19 20 21 22 23 24 25
TriQuint’s TQ2061 is a high-frequency clock generator. It utilizes a 25 MHz
to 35 MHz TTL input to generate a 500 MHz to 700 MHz PECL output. The
TQ2061 has a completely self-contained Phase-Locked Loop (PLL) running
at 500 MHz to 700 MHz. This stable PLL allows for a low period-to-period
output jitter of 70 ps (max), and enables tight duty cycle control of 55% to
45% (worst case).
The TQ2061 provides optional 200-ohm on-chip pull-down resistors which
are useful if the output is AC-coupled to the device being driven. In order
to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN),
and pin 23 (PDR1) should be connected to pin 22 (Q).
Features
Output frequency range:
500 MHz to 700 MHz
One differential PECL output:
600 mV (min) swing
Common-mode voltage:
VDD –1.2 V (max),
VDD –1.6 V (min)
Period-to-period output jitter:
25 ps peak-to-peak (typ)
70 ps peak-to-peak (max)
Reference clock input:
25 MHz to 35 MHz TTL-level
crystal oscillator
Self-contained loop filter
Optional 200 pull-down
resistors for AC-coupled outputs
+5 V power supply
28-pin J-lead surface-mount
package
Ideal for designs based on DEC
Alpha AXPprocessors
Various test modes on the chip simplify debug and testing of systems by
slowing the clock output or by bypassing the PLL.
For additional information and latest specifications, see our website: www.triquint.com
1

TQ2061
TQ2061
Figure 2. Simplified Block Diagram
REFCLK
(25MHz to
35 MHz)
TESTIN
Phase
TEST1
TEST2
Control
VCO
MUX : 20
MUX
QN
(500 MHz
to
Q 700 MHz)
Table 1. Mode Selection
Mode
TEST1
TEST2
1 (Test)
2 (Test)
3 (Test)
4 (Bypass)
5 (Normal)
00
01
10
11
11
Notes: 1. In mode 3, TESTIN may be used to bypass the PLL.
2. REFCLK = 25 MHz to 35 MHz.
3. Q, QN = 500 MHz to 700 MHz.
TESTIN 1
“don’t care”
“don’t care”
fTESTCLK
0
1
REFCLK
fREFCLK
“don't care”
“don't care”
fREFCLK
fREFCLK
Q, QN
fREFCLK2
0, 1
fTESTCLK
fREFCLK
20 x fREFCLK3
Figure 3. Recommended Layout
(Not to scale)
REFCLK
(from TTLoscillator)
GND
0.1 µF
(From TTL Oscillator)
Pin 1 VDD
GND
0.1 µF
VDD
GND
Q 50 OHMS
QN
VDD
0.1 µF
GND
2 For additional information and latest specifications, see our website: www.triquint.com


Features T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ2061 Figure 1. Pi nout Diagram TESTIN REFCLK High-Freque ncy Clock Generator 4 GND GND NC 6 11 10 NC 9 8 7 VDD NC TEST1 TEST2 NC NC GND NC 5 12 Phase NC NC NC 1 3 14 15 16 17 18 19 20 21 Control VCO ÷20 Features • Output frequency ra nge: 500 MHz to 700 MHz • One differe ntial PECL output: 600 mV (min) swing Common-mode voltage: VDD –1.2 V (m ax), VDD –1.6 V (min) • Period-to-p eriod output jitter: 25 ps peak-to-peak (typ) 70 ps peak-to-peak (max) • Ref erence clock input: 25 MHz to 35 MHz TT L-level crystal oscillator • Self-con tained loop filter • Optional 200 Ω pull-down resistors for AC-coupled out puts • +5 V power supply • 28-pin J -lead surface-mount package • Ideal f or designs based on DEC Alpha AXP™ pr ocessors MUX 3 2 MUX 1 NC 28 NC 27 NC 26 22 23 24 25 AGND EVDD PDR2 QN PDR1 GND Q TriQuint’s TQ2061 is a high-frequency clock generator. It utilizes a 25 MHz to 35 MHz TTL input to generate a 5.
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