TQ9303 Channel Encoder/Decoder Datasheet

TQ9303 Datasheet, PDF, Equivalent


Part Number

TQ9303

Description

Fibre Channel Encoder/Decoder

Manufacture

TriQuint Semiconductor

Total Page 25 Pages
Datasheet
Download TQ9303 Datasheet


TQ9303
TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. TQ9303 Block Diagram
TQ9303
Data
32
Parity
4
Control
11
HOST
Data
32
Parity
4
Control
12
Data
10
Control
2
TQ9501
or
GA9101
Tx
2
Optical Tx
or
Copper
Interface
TQ9303
ENDEC
2
TQ9502
Optical Rx
Data or
or
10 GA9102
Copper
Control Rx 2 Interface
2
The TQ9303 ENDEC (ENcoder/DECoder) implements 8b/10b encoding
and decoding, ordered set encoding and decoding, and parity checking
and generation as defined in the Fibre Channel Physical Signaling
Interface Standard (FC-PH). The ENDEC fully implements the FC-1 layer
of the Fibre Channel Standard. Implemented in a 0.8-micron CMOS
process, the ENDEC also performs 32-bit CRC checking and generation
as defined in the FC-2 layer of the Fibre Channel specification.
The TQ9303 ENDEC interfaces directly to TriQuint’s FC-0 layer Fibre Channel
Transmitter (Tx) and Receiver (Rx) chipsets at the speeds shown below:
FC Rate
FC-266
FC-531
FC-1063
Transmitter
GA9101
TQ9501
TQ9501
Receiver
GA9102
TQ9502
TQ9502
Data Rate (Mbaud)
194–266
500–625
1000–1250
Triquint’s Transmitter and Receiver devices are designed with TriQuint’s
proprietary 0.7-micron GaAs process. The Tx and Rx interface directly to
copper-based electrical media or to a fiber-optic module. The Transmitter
performs parallel-to-serial conversion on the encoded data and generates
the internal high-speed clock for the serial output data stream. The Receiver
recovers the clock and data from the input serial stream, performs serial-
to-parallel conversion, and detects and aligns on the K28.5 character.
Fibre Channel
Encoder/Decoder
Features
• Compliant with ANSI X3T11
Fibre Channel Standard
• Full implementation of
Fibre Channel’s FC-1 layer
• Interfaces directly with
TriQuint’s GA9101/GA9102
and TQ9501/TQ9502 FC-0
Fibre Channel chipsets
• Suitable for proprietary serial
links (virtual ribbon cable)
• Implements 8b/10b encoding
and decoding
• Implements ordered set
encoding and decoding
• Checks and generates 32-bit
CRC and parity
10-bit TTL-compatible interface
to Transmitter and Receiver
• 32-bit interface to the host
• Fully synchronous operation
• 160-pin PQFP
For additional information and latest specifications, see our website: www.triquint.com
1

TQ9303
TQ9303
Fibre Channel provides a transport vehicle for Intelligent
Peripheral Interface (IPI) and Small Computer System
Interface (SCSI) upper layer command sets, High-
Performance Parallel Interface (HIPPI) data link layer,
and other user-defined command sets. Fibre Channel
replaces the SCSI, IPI, and HIPPI physical interfaces
with a protocol-efficient alternative that provides
performance improvements over distance and speed.
Fibre Channel is optimized for predictable transfers of
large blocks of data such as those used in file transfers
between processors (such as super computers, main-
frames, and super minis), storage systems (such as disk
and tape drives), communications devices, and output-
only devices (such as laser printers and raster scan
graphics terminals). The Fibre Channel protocol is
implemented in hardware, making it simple, efficient,
and robust.
The lower level physical interface is decoupled from the
higher level protocol, allowing Fibre Channel to be config-
ured with various topologies. Point-to-point, multi-drop
bus, ring, and cross-point switch topologies are permit-
ted in Fibre Channel, optimizing it for specific applications.
Fibre Channel supports distances up to 10␣ Km at baud
rates of 132.8125␣ Mbaud to 1.0625␣ Gbaud. Coax and
STP (Shielded Twisted Pair) are used at lower data
rates and shorter distances, while fiber-optic cables are
used for higher data rates and longer distances.
Figure 2. TQ9303 ENDEC Block Diagram
CTXD0..31
32
CTXC0,
CTXC1,
CTXP0..3,
CTXRAWA,
CTXRAWB
CTXRAW,
CTXPENN,
CTXPMODE
CTXPERR
CTXCERR
CTXCLK
CTXWREF
8
3
RESETN
RXERROR
CRXD0..31
32
CRXP0..3,
CRXS0,
CRXS2..4
RAW Rx,
RXPMODE
CRXS1
CRXS5
WRDSYNC
RXCKPH0,1
CRXCLK
8
2
40 40
17
20 17
Word-to-
Half-Word
Shifter
Mux 17
8b/10b
Encoder
20
Mux
Half-Word-
to-Byte
10
Shifter
Parity
Checker/
Generator
Ordered Set
Encoder
32-BIT CRC
Generator/
Checker
ENCODER SECTION
Word Half Word Byte
Clk Clk Clk
Clock Generator
36
40
Half-Word-
to-Word
20
Mux
4 Shifter
DECODER SECTION
1
20
16
16
1
3
10b/8b
Decoder
20 Byte-to-
Half-Word
Shifter
Parity
Generator
32-Bit CRC
Checker
Ordered Set
Decoder
Line State
Decoder
Word Sync
Detector
Word Half Word Byte
Clk Clk Clk
2 Clock Generator
10
BTXD0..9
BTXCKIN
BTXCKOUT
10 BRXD0..9
BRXCLK
BRXSYNC
2 For additional information and latest specifications, see our website: www.triquint.com


Features T R I Q U I N T S E M I C O N D U C T O R, I N C . Figure 1. TQ9303 Bl ock Diagram Data Data 32 Parity 4 Contr ol 11 HOST Data 32 Parity 4 Control 12 Data 10 Control 2 TQ9502 or GA9102 Rx O ptical Rx or Copper Interface TQ9303 EN DEC 2 10 Control 2 TQ9501 or GA9101 Tx 2 Optical Tx or Copper Interface TQ930 3 Fibre Channel Encoder/Decoder Feature s • Compliant with ANSI X3T11 Fibre C hannel Standard • Full implementation of Fibre Channel’s FC-1 layer • In terfaces directly with TriQuint’s GA9 101/GA9102 and TQ9501/TQ9502 FC-0 Fibre Channel chipsets • Suitable for prop rietary serial links (virtual ribbon ca ble) • Implements 8b/10b encoding and decoding • Implements ordered set en coding and decoding • Checks and gene rates 32-bit CRC and parity • 10-bit TTL-compatible interface to Transmitter and Receiver • 32-bit interface to t he host • Fully synchronous operation • 160-pin PQFP 2 The TQ9303 ENDEC (ENcoder/DECoder) implements 8b/10b encoding and decoding, ordered set encoding and decod.
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